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1. 发明公开

US20230402364A1 LEADFRAME WITH A METAL OXIDE COATING AND METHOD OF FORMING THE SAME 审中-公开
公开(公告)号：US20230402364A1
公开(公告)日：2023-12-14
申请号：US18451022
申请日：2023-08-16
申请人： STMicroelectronics International N.V.
发明人： Luca Maria Carlo DI DIO
IPC分类号： H01L23/498 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495
CPC分类号： H01L23/49872 , H01L23/49861 , H01L21/4846 , H01L21/565 , H01L23/3114 , H01L23/49586 , H01L23/49582
摘要： A leadframe including a metal oxide layer on at least a portion of the leadframe are disclosed. More specifically, leadframes with a metal layer and a metal oxide layer formed on one or more leads before a tin finish plating layer is formed are described. The layers of metal and metal oxide between the one or more leads and the tin finish plating layer reduce the formation of tin whiskers, thus reducing the likelihood of shorting and improving the overall reliability of the package structure and device produced.

2. 发明公开

US20230369256A1 Multi-Device Power Module Arrangement 审中-公开
公开(公告)号：US20230369256A1
公开(公告)日：2023-11-16
申请号：US17742767
申请日：2022-05-12
申请人： Infineon Technologies AG
发明人： Kushal Kshirsagar , Eung San Cho , Danny Clavette , Wenkang Huang , Angela Kessler
IPC分类号： H01L23/66 , H01L23/367 , H01L23/13 , H05K1/11 , H05K3/30 , H01L23/495 , H01L23/498
CPC分类号： H01L23/66 , H01L23/3675 , H01L23/13 , H05K1/111 , H05K3/301 , H01L23/49503 , H01L23/49541 , H01L23/49872 , H05K2201/10431 , H05K2201/1003
摘要： A semiconductor assembly includes a carrier including a dielectric substrate and a plurality of contact pads disposed on an upper surface of the carrier, first and second surface mount packages mounted on the carrier, first and second discrete inductors respectively mounted over the first and second surface mount packages, wherein the first and second surface mount packages each comprise lower surface terminals that face and electrically connect with the contact pads from the carrier, wherein the first and second surface mount packages each comprise an upper side that faces away from the carrier, and wherein the first and second discrete inductors are respectively thermally coupled to the upper sides of the first and second surface mount packages.

3. 发明授权

US09673206B2 Buried hard mask for embedded semiconductor device patterning 有权
公开(公告)号：US09673206B2
公开(公告)日：2017-06-06
申请号：US15133026
申请日：2016-04-19
申请人： Cypress Semiconductor Corporation
发明人： Scott A. Bell , Angela Tai Hui , Simon S. Chan
IPC分类号： H01L27/11521 , H01L27/11546 , H01L21/8238 , H01L23/498 , H01L21/3213
CPC分类号： H01L27/11521 , H01L21/32139 , H01L21/823828 , H01L21/823857 , H01L23/49811 , H01L23/49844 , H01L23/49872 , H01L23/49894 , H01L27/11546
摘要： Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device comprises a first region, a second region, a first polysilicon region, and a second polysilicon region. The first polysilicon region is formed over the first and second regions of the semiconductor device. Portions of the first and polysilicon layers that are uncovered by either of a first mask and a second mask are removed. The first mask is formed on the first polysilicon layer and the second mask is formed on the second polysilicon layer in the first region and not on in the second region.

4. 发明申请

US20160242294A1 ELECTRONIC DEVICE 审中-公开
标题翻译：电子设备
公开(公告)号：US20160242294A1
公开(公告)日：2016-08-18
申请号：US15044878
申请日：2016-02-16
申请人： ROHM CO., LTD.
发明人： Hideaki YANAGIDA
IPC分类号： H05K1/18
CPC分类号： H01L23/49872 , H01L21/486 , H01L23/13 , H01L23/147 , H01L23/3121 , H01L23/49827 , H01L2224/16235 , H01L2924/15156 , H01L2924/15313
摘要： The present disclosure provides an electronic device suitable for miniaturization. The present electronic device includes: a substrate (1), having a main surface (111) and a back surface (112) facing opposite sides with each other in a thickness direction, wherein the substrate comprises a semiconductor material; an electronic component (8), which is disposed over the substrate (1); and a conductive layer (3), which is electrically connected with the electronic component (8); wherein a recess for disposing the component (14) and a through recess (17) are formed in the substrate, in which recess for disposing the component (14) is recessed from the main surface (111), and the through recess (17) penetrates from the recess for disposing the component (14) to the back surface (112); the electronic component (8) is disposed over the recess for disposing the component (14); a metal-filled portion (4) is formed in the through recess (17), wherein the metal-filled portion blocks at least the bottom of the through recess (17) and is filled with a metal material; and the conductive layer (3) is formed at least from the through recess (17) to the back surface (112).
摘要翻译：本公开提供了适合于小型化的电子设备。本电子设备包括：基板（1），其具有在厚度方向上彼此相对的主表面（111）和背面（112），其中所述基板包括半导体材料; 设置在所述基板（1）上方的电子部件（8）; 和与电子部件（8）电连接的导电层（3）。其特征在于，在所述基板上形成有用于配置所述部件（14）和贯通凹部（17）的凹部，在所述基板中，用于配置所述部件（14）的凹部从所述主表面（111）凹进，从所述凹部穿透以将所述部件（14）设置到所述后表面（112）; 电子部件（8）设置在用于设置部件（14）的凹部上方。在所述贯通凹部（17）中形成金属填充部（4），所述金属填充部至少阻挡所述贯通凹部（17）的底部并填充有金属材料。并且所述导电层（3）至少从所述贯通凹部（17）形成到所述后表面（112）。

5. 发明申请

US20160118271A1 METHOD OF FABRICATING SEMICONDUCTOR PACKAGE HAVING AN INTERPOSER STRUCTURE 审中-公开
标题翻译：制造具有插入式结构的半导体封装的方法
公开(公告)号：US20160118271A1
公开(公告)日：2016-04-28
申请号：US14986903
申请日：2016-01-04
申请人： Siliconware Precision Industries Co., Ltd.
发明人： Kuan-Wei Chuang , Chun-Tang Lin , Yi-Chian Liao , Yi-Che Lai
IPC分类号： H01L21/48 , H01L21/683 , H01L21/78 , H01L23/498 , H01L23/00 , H01L21/311 , H01L21/56 , H01L25/00
CPC分类号： H01L21/486 , H01L21/31111 , H01L21/4853 , H01L21/563 , H01L21/6835 , H01L21/78 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/49872 , H01L24/03 , H01L24/08 , H01L24/11 , H01L24/17 , H01L24/97 , H01L25/50 , H01L2224/02317 , H01L2224/02372 , H01L2224/03002 , H01L2224/08235 , H01L2224/16 , H01L2224/16245 , H01L2924/351 , H01L2924/00
摘要： A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.
摘要翻译：提供一种制造半导体封装的方法，包括：将衬底切割成多个中介层; 将所述插入件布置在载体的多个开口中，其中所述开口彼此间隔一定距离; 形成第一密封剂以封装所述插入件; 移除载体; 以及在每个所述插入件上设置至少一个半导体元件。通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止由于不良插入件浪费完成的封装。

6. 发明授权

US09257381B2 Semiconductor package, and interposer structure of the semiconductor package 有权
标题翻译：半导体封装和半导体封装的内插器结构
公开(公告)号：US09257381B2
公开(公告)日：2016-02-09
申请号：US13722017
申请日：2012-12-20
申请人： Siliconware Precision Industries Co., Ltd.
发明人： Kuan-Wei Chuang , Chun-Tang Lin , Yi-Chian Liao , Yi-Che Lai
IPC分类号： H01L23/14 , H01L23/498 , H01L21/78 , H01L23/00 , H01L21/48
CPC分类号： H01L21/486 , H01L21/31111 , H01L21/4853 , H01L21/563 , H01L21/6835 , H01L21/78 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/49872 , H01L24/03 , H01L24/08 , H01L24/11 , H01L24/17 , H01L24/97 , H01L25/50 , H01L2224/02317 , H01L2224/02372 , H01L2224/03002 , H01L2224/08235 , H01L2224/16 , H01L2224/16245 , H01L2924/351 , H01L2924/00
摘要： A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.
摘要翻译：提供一种制造半导体封装的方法，包括：将衬底切割成多个中介层; 将所述插入件布置在载体的多个开口中，其中所述开口彼此间隔一定距离; 形成第一密封剂以封装所述插入件; 移除载体; 以及在每个所述插入件上设置至少一个半导体元件。通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止由于不良插入件浪费完成的封装。

7. 发明申请

US20140070424A1 SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE, AND INTERPOSER STRUCTURE OF THE SEMICONDUCTOR PACKAGE 有权
标题翻译：半导体封装，制造半导体封装的方法和半导体封装的间隔器结构
公开(公告)号：US20140070424A1
公开(公告)日：2014-03-13
申请号：US13722017
申请日：2012-12-20
申请人： SILICONWARE PRECISION INDUSTRIES CO., LTD.
发明人： Kuan-Wei Chuang , Chun-Tang Lin , Yi-Chian Liao , Yi-Che Lai
IPC分类号： H01L23/498 , H01L21/78
CPC分类号： H01L21/486 , H01L21/31111 , H01L21/4853 , H01L21/563 , H01L21/6835 , H01L21/78 , H01L23/147 , H01L23/49816 , H01L23/49827 , H01L23/49872 , H01L24/03 , H01L24/08 , H01L24/11 , H01L24/17 , H01L24/97 , H01L25/50 , H01L2224/02317 , H01L2224/02372 , H01L2224/03002 , H01L2224/08235 , H01L2224/16 , H01L2224/16245 , H01L2924/351 , H01L2924/00
摘要： A method of fabricating a semiconductor package is provided, including: cutting a substrate into a plurality of interposers; disposing the interposers in a plurality of openings of a carrier, wherein the openings are spaced from one another by a distance; forming a first encapsulant to encapsulate the interposers; removing the carrier; and disposing at least a semiconductor element on each of the interposers. By cutting the substrate first, good interposers can be selected and rearranged such that finished packages can be prevented from being wasted due to inferior interposers.
摘要翻译：提供一种制造半导体封装的方法，包括：将衬底切割成多个中介层; 将所述插入件布置在载体的多个开口中，其中所述开口彼此间隔一定距离; 形成第一密封剂以封装所述插入件; 移除载体; 以及在每个所述插入件上设置至少一个半导体元件。通过首先切割基板，可以选择和重新布置良好的插入件，从而可以防止由于不良插入件浪费完成的封装。

8. 发明申请

US20120132460A1 LAMINATED WIRING BOARD 有权
标题翻译：层压接线板
公开(公告)号：US20120132460A1
公开(公告)日：2012-05-31
申请号：US13378110
申请日：2010-06-03
申请人： Yoshihisa Warashina
发明人： Yoshihisa Warashina
IPC分类号： H05K1/03
CPC分类号： H01L23/147 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49872 , H01L27/14636 , H01L2224/16225 , H01L2924/157 , H01L2924/3011
摘要： In a multilayer wiring board 1, a low resistance silicon substrate 2 having a predetermined resistivity and a high resistance silicon substrate 4 having a resistivity higher than the predetermined resistivity are stacked while interposing an insulating layer 3 therebetween. The low resistance silicon substrate 2 is provided with an electric passage part 6 surrounded by a ring-shaped groove 5, while a wiring film 13 electrically connected to the electric passage part 6 through an opening 8 of the insulating layer 3 is disposed on a rear face 4b of the high resistance silicon substrate 4 and an inner face 11a of a recess 11. Since the high resistance silicon substrate 4 is thus provided with the wiring film 13, an optical semiconductor element 20 and an electronic circuit element 30 which differ from each other in terms of the number and positions of electrode pads can be electrically connected to each other on the front and rear face sides of the multilayer wiring board 1.
摘要翻译：在多层布线基板1中，层叠具有预定电阻率的低电阻硅基板2和电阻率高于预定电阻率的高电阻硅基板4，同时在其间插入绝缘层3。低电阻硅基板2设置有被环状槽5包围的电通路部分6，而通过绝缘层3的开口8电连接到电通路部分6的布线膜13设置在后部高电阻硅衬底4的表面4b和凹部11的内表面11a。由于高电阻硅衬底4因此设置有布线膜13，光学半导体元件20和电子电路元件30与每个电极焊盘的数量和位置方面的其他方面可以在多层布线基板1的正面和背面侧彼此电连接。

9. 发明申请

US20040180524A1 Shielded multi-conductor interconnect bus for MEMS 审中-公开
公开(公告)号：US20040180524A1
公开(公告)日：2004-09-16
申请号：US10815137
申请日：2004-03-31
发明人： Murray Steven Rodgers , Stephen Matthew Barnes
IPC分类号： H01L021/4763
CPC分类号： B81B7/0006 , G02B26/0841 , H01L23/147 , H01L23/49872 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： A shielded multi-conductor interconnect bus for use in interconnecting MEM devices with control signal sources or the like and a method of fabricating a shielded multi-conductor interconnect bus are disclosed. In one embodiment, a shielded interconnect bus formed on a substrate (20) includes a plurality of electrically conductive lines (42) arranged in sets of one, two or more conductive lines between electrically conductive shield walls (46, 66). The electrically conductive lines (42) are surrounded by layers of dielectric material (30, 50). An electrically conductive shield (78) overlies the electrically conductive lines (42) and electrically conductive shield walls (46, 66).

10. 发明授权

US06559528B2 Semiconductor device and method for the fabrication thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06559528B2
公开(公告)日：2003-05-06
申请号：US09785503
申请日：2001-02-20
申请人： Kazumi Watase , Hiroaki Fujimoto , Ryuichi Sahara , Nozomi Shimoishizaka , Takahiro Kumakawa , Kazuyuki Kaino , Yoshifumi Nakamura
发明人： Kazumi Watase , Hiroaki Fujimoto , Ryuichi Sahara , Nozomi Shimoishizaka , Takahiro Kumakawa , Kazuyuki Kaino , Yoshifumi Nakamura
IPC分类号： H01L23498
CPC分类号： H01L24/97 , H01L23/3114 , H01L23/3121 , H01L23/49872 , H01L24/45 , H01L24/48 , H01L24/94 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/05599 , H01L2224/05647 , H01L2224/12105 , H01L2224/16145 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73209 , H01L2224/85399 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2924/00015 , H01L2224/45015 , H01L2924/207
摘要： Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.
摘要翻译：公开了一种半导体器件10，其包括具有第一元件电极12的布置的第一半导体元件11，具有第二元件电极14的布置的第二半导体元件13，将第一元件电极的部分12b电连接在一起的连接构件15 12和第二元件电极14，覆盖第一半导体元件11的主表面11a和第二半导体元件13的背面13b的绝缘层17，形成在绝缘层17上并电连接到第二半导体元件13的布线层22的布线层22。露出在开口部分21中的第一元件电极部分12b和作为布线层22的一部分形成在绝缘层17上的外部电极23。

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