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51. 发明申请

US20100032761A1 SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US20100032761A1
公开(公告)日：2010-02-11
申请号：US12188381
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

52. 发明授权

US07571637B2 Design structure for an on-chip real-time moisture sensor for and method of detecting moisture ingress in an integrated circuit chip 失效
标题翻译：片上实时湿度传感器的设计结构和集成电路芯片中水分进入检测方法
公开(公告)号：US07571637B2
公开(公告)日：2009-08-11
申请号：US11926241
申请日：2007-10-29
申请人： Fen Chen , Kai D. Feng
发明人： Fen Chen , Kai D. Feng
IPC分类号： G01N5/02
CPC分类号： G01N27/223
摘要： A design structure for an on-chip real-time moisture detection circuitry for monitoring ingress of moisture into an integrated circuit chip during the operational lifetime of the chip. The moisture detection circuitry includes one or more moisture-sensing units and a common moisture monitor for monitoring the state of each moisture-sensing units. The moisture monitor can be configured to provided a real-time moisture-detected signal for signaling that moisture ingress into the integrated circuit chip has occurred.
摘要翻译：一种片上实时水分检测电路的设计结构，用于在芯片的使用寿命期间监测水分进入集成电路芯片的情况。湿度检测电路包括一个或多个湿度感测单元和用于监测每个湿度感测单元的状态的公共湿度监视器。水分监测器可以被配置为提供实时湿度检测信号，用于发信号通知已经发生湿气进入集成电路芯片。

53. 发明申请

US20090113361A1 Design Structure for an Automated Real-Time Frequency Band Selection Circuit for use with a Voltage Controlled Oscillator 失效
标题翻译：用于电压控制振荡器的自动实时频段选择电路的设计结构
公开(公告)号：US20090113361A1
公开(公告)日：2009-04-30
申请号：US11928093
申请日：2007-10-30
申请人： Kai D. Feng , Anjali R. Malladi
发明人： Kai D. Feng , Anjali R. Malladi
IPC分类号： G06F17/50 , H03L7/099
CPC分类号： H03L7/099 , H03L7/10 , H03L2207/06
摘要： A design structure for an integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.
摘要翻译：一种用于集成电路的设计结构，包括响应于压控振荡器（VCO）频带选择电路的锁相环（PLL）电路，其实时提供自动频带选择以解决运行时间变化，例如功率供应和温度随时间变化。 PLL包括电荷泵和LC槽电路，其基于由电荷泵提供的VCO控制电压信号提供自动频带选择。

54. 发明申请

US20080233681A1 Design of BEOL Patterns to Reduce the Stresses on Structures Below Chip Bondpads 失效
标题翻译：设计BEOL模式以减少芯片贴片下方结构的应力
公开(公告)号：US20080233681A1
公开(公告)日：2008-09-25
申请号：US12133442
申请日：2008-06-05
申请人： Elie Awad , Mariette A. Awad , Kai D. Feng
发明人： Elie Awad , Mariette A. Awad , Kai D. Feng
IPC分类号： H01L21/00
CPC分类号： H01L24/02 , H01L23/562 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/3025
摘要： A semiconductor structure comprising a substrate including a first layer comprising a first material having a first modulus of elasticity; a first structure comprising a conductor and formed within the substrate, the first structure having an upper surface; and a stress diverting structure proximate the first structure and within the first layer, the stress diverting structure providing a low mechanical stress region at the upper surface of the first structure when a physical load is applied to the first structure, wherein said low mechanical stress region comprises stress values below the stress values in areas not protected by the stress diverting structure. The stress diverting structure comprises a second material having a second modulus of elasticity less than the first modulus of elasticity, the second material selectively formed over the upper surface of the first structure for diverting mechanical stress created by the physical load applied to the first structure.
摘要翻译：一种半导体结构，包括：基板，包括第一层，所述第一层包括具有第一弹性模量的第一材料; 包括导体并形成在所述基板内的第一结构，所述第一结构具有上表面; 以及靠近所述第一结构并且在所述第一层内的应力转向结构，所述应力转向结构在向所述第一结构施加物理载荷时在所述第一结构的上表面处提供低机械应力区域，其中所述低机械应力区域包括低于应力转移结构保护区域的应力值。应力转向结构包括具有小于第一弹性模量的第二弹性模量的第二材料，第二材料选择性地形成在第一结构的上表面上，用于转移由施加到第一结构的物理负载产生的机械应力。

55. 发明申请

US20080197337A1 PHASE-CHANGE TaN RESISTOR BASED TRIPLE-STATE/MULTI-STATE READ ONLY MEMORY 有权
标题翻译：基于相位变化的电阻基于三态/多状态只读存储器
公开(公告)号：US20080197337A1
公开(公告)日：2008-08-21
申请号：US12109085
申请日：2008-04-24
申请人： John M. Aitken , Fen Chen , Kai D. Feng
发明人： John M. Aitken , Fen Chen , Kai D. Feng
IPC分类号： H01L47/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C11/5692 , G11C13/0004 , G11C17/16 , G11C17/18 , H01L27/101 , H01L27/2409 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/145
摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.
摘要翻译：本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。读写电路和操作也在本申请中提供。

56. 发明授权

US07381981B2 Phase-change TaN resistor based triple-state/multi-state read only memory 有权
标题翻译：相变TaN电阻器基于三态/多态只读存储器
公开(公告)号：US07381981B2
公开(公告)日：2008-06-03
申请号：US11161332
申请日：2005-07-29
申请人： John M. Aitken , Fen Chen , Kai D. Feng
发明人： John M. Aitken , Fen Chen , Kai D. Feng
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： G11C11/56 , G11C11/5678 , G11C11/5692 , G11C13/0004 , G11C17/16 , G11C17/18 , H01L27/101 , H01L27/2409 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/145
摘要： The present invention relates to a nonvolatile memory such as, for example a ROM or an EPROM, in which the information density of the memory is increased relative to a conventional nonvolatile memory that includes two logic state devices. Specifically, the nonvolatile memory of the present invention includes a SiN/TaN/SiN thin film resistor embedded within a material having a thermal conductivity of about 1 W/m-K or less; and a non-linear Si-containing device coupled to the resistor. Read and write circuits and operations are also provided in the present application.
摘要翻译：本发明涉及诸如ROM或EPROM的非易失性存储器，其中存储器的信息密度相对于包括两个逻辑状态器件的常规非易失性存储器而增加。具体地，本发明的非易失性存储器包括嵌入在热导率为约1W / m-K以下的材料中的SiN / TaN / SiN薄膜电阻器; 以及耦合到电阻器的非线性含Si器件。读写电路和操作也在本申请中提供。

57. 发明授权

US07129821B2 Communication systems and methods using microelectronics power distribution network 失效
标题翻译：通信系统和方法采用微电子配电网络
公开(公告)号：US07129821B2
公开(公告)日：2006-10-31
申请号：US10711082
申请日：2004-08-20
申请人： Serafino Bueti , Adam J. Courchesne , Kai D. Feng , Kenneth J. Goodnow , Gregory J. Mann , Scott T. Vento
发明人： Serafino Bueti , Adam J. Courchesne , Kai D. Feng , Kenneth J. Goodnow , Gregory J. Mann , Scott T. Vento
IPC分类号： G05B11/01
CPC分类号： H04B3/54 , H04B2203/5416
摘要： A communication system, which includes a microelectronics chip including a power distribution network; a transmitter operatively configured to generate a communication signal and provide the communication signal to the power distribution network; and a receiver operatively configured to receive the communication signal from the power distribution network. A method is also provided for transmitting a communication signal via a power distribution network of a microelectronics chip.
摘要翻译：一种通信系统，其包括具有配电网络的微电子芯片; 发射机，可操作地配置为产生通信信号并将所述通信信号提供给所述配电网络; 以及可操作地配置为从所述配电网接收所述通信信号的接收器。还提供了一种通过微电子芯片的配电网传送通信信号的方法。

58. 发明授权

US5465143A ADP switch and adjustable data acquisition window 失效
标题翻译： ADP开关和可调数据采集窗口
公开(公告)号：US5465143A
公开(公告)日：1995-11-07
申请号：US186966
申请日：1994-01-27
申请人： Ching Chu , David Liao , Kai D. Feng
发明人： Ching Chu , David Liao , Kai D. Feng
IPC分类号： G01M11/00 , G01N21/88
CPC分类号： G01M11/3145
摘要： An OTDR to examine light reflected from an optic fibre has an amplification stage that operates in either a high gain or low gain mode. To avoid saturation of the amplifier in the high gain mode, the trace is examined to identify the location of spikes and a switch is controlled to connect the amplifier to the signal after the occurrence of the spike.
摘要翻译：检查从光纤反射的光的OTDR具有以高增益或低增益模式工作的放大级。为了避免放大器在高增益模式下饱和，检查迹线以识别尖峰的位置，并且控制开关以在发生尖峰之后将放大器连接到信号。

59. 发明授权

US08890556B2 Real-time on-chip EM performance monitoring 有权
标题翻译：实时片上EM性能监控
公开(公告)号：US08890556B2
公开(公告)日：2014-11-18
申请号：US13282090
申请日：2011-10-26
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187 , G01R31/30
CPC分类号： G01R31/3004
摘要： An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.
摘要翻译：用于监测电迁移（EM）性能的集成电路，测试结构和方法。描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。

60. 发明申请

US20140035670A1 FET PAIR BASED PHYSICALLY UNCLONABLE FUNCTION (PUF) CIRCUIT WITH A CONSTANT COMMON MODE VOLTAGE 有权
标题翻译：具有恒定通用模式电压的基于FET对的物理不可靠功能（PUF）电路
公开(公告)号：US20140035670A1
公开(公告)日：2014-02-06
申请号：US13566805
申请日：2012-08-03
申请人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
发明人： Howard H. Chi , Haitao O. Dai , Kai D. Feng , Donald J. Papae
IPC分类号： H03F3/45
CPC分类号： G06F7/588 , G09C1/00 , H04L9/0866 , H04L9/3278 , H04L2209/12
摘要： A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.
摘要翻译：公开了一种具有恒定共模电压的物理不可克隆功能（PUF）电路和使用方法的FET对。电路包括第一n型场效应晶体管（NFET）和第二NFET。电路还包括通过第一p型场效应晶体管（PFET）耦合到第一NFET的第一负载电阻器和通过第二PFET耦合到第二NFET的第二负载电阻器。电路还包括闭环，其中闭环产生恒定的共模电压。

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