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51. 发明申请

US20050269482A1 Active pixel sensor cell with integrating varactor and method for using such cell 有权
标题翻译：具有积分变容二极管的有源像素传感器单元和使用这种单元的方法
公开(公告)号：US20050269482A1
公开(公告)日：2005-12-08
申请号：US10863058
申请日：2004-06-08
申请人： Peter Hopper , Philipp Lindorfer , Mark Poulter , Yuri Mirgorodski
发明人： Peter Hopper , Philipp Lindorfer , Mark Poulter , Yuri Mirgorodski
IPC分类号： H01L27/146 , H04N5/353 , H04N5/361 , H04N5/3745 , H01L27/00
CPC分类号： H01L27/14609 , H04N5/35572 , H04N5/361 , H04N5/37452
摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
摘要翻译：包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管，用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。在曝光间隔期间，可以将光电二极管暴露于光子，以在光电二极管的第一节点处累积次曝光电荷序列。在曝光间隔的不同子曝光间隔期间，每个次曝光电荷在第一节点处累积。在每个复位间隔的每一个期间复位光电二极管，每个复位间隔发生在不同的次曝光间隔之前。指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言，其中曝光电荷指示所有次曝光电荷的总和。

52. 发明授权

US08669157B2 Non-volatile memory cell having a heating element and a substrate-based control gate 有权
标题翻译：具有加热元件和基于基板的控制栅极的非易失性存储单元
公开(公告)号：US08669157B2
公开(公告)日：2014-03-11
申请号：US13477019
申请日：2012-05-21
申请人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
发明人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7841 , H01L29/7881
摘要： The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
摘要翻译：可以通过利用局部加热元件来使得非易失性存储器（NVM）被编程和擦除的次数大大增加，所述局部加热元件在NVM被编程和擦除时使隧道电荷载体损坏的氧化物退火。在编程和擦除之前，加热元件的热量时，编程和擦除电压也会降低。

53. 发明授权

US08207578B2 Method of forming a region of graded doping concentration in a semiconductor device and related apparatus 有权
标题翻译：在半导体器件和相关装置中形成渐变掺杂浓度区域的方法
公开(公告)号：US08207578B2
公开(公告)日：2012-06-26
申请号：US13156184
申请日：2011-06-08
申请人： William French , Erika Mazotti , Yuri Mirgorodski
发明人： William French , Erika Mazotti , Yuri Mirgorodski
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/2253 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.
摘要翻译：用于形成半导体器件的掺杂区域的方法包括用掩模掩蔽衬底的一部分。掩模被配置为在掺杂区域内产生渐变掺杂分布。该方法还包括使用掩模执行植入物以在衬底中产生掺杂区域和未掺杂区域。该方法还包括扩散掺杂区域以在掺杂区域中产生渐变掺杂分布。掩模可以包括具有分布在整个光致抗蚀剂材料中的开口的第一区域，其中开口的尺寸和间隔变化。掩模还可以包括具有分布在整个开放区域中的光致抗蚀剂材料块的第二区域，其中光刻胶块的尺寸和间距变化。扩散掺杂区域可以包括施加高温退火以使掺杂和未掺杂区域平滑以产生线性渐变的掺杂分布。

54. 发明授权

US07919807B1 Non-volatile memory cell with heating element 有权
标题翻译：带加热元件的非易失性存储单元
公开(公告)号：US07919807B1
公开(公告)日：2011-04-05
申请号：US11729710
申请日：2007-03-29
申请人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
发明人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7841 , H01L29/7881
摘要： The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
摘要翻译：可以通过利用局部加热元件来使得非易失性存储器（NVM）被编程和擦除的次数大大增加，所述局部加热元件在NVM被编程和擦除时使隧道电荷载体损坏的氧化物退火。在编程和擦除之前，加热元件的热量时，编程和擦除电压也会降低。

55. 发明申请

US20080032467A1 Integrated Circuit with Metal Heat Flow Path Coupled to Transistor and Method for Manufacturing Such Circuit 有权
标题翻译：具有耦合到晶体管的金属热流路的集成电路及其制造方法
公开(公告)号：US20080032467A1
公开(公告)日：2008-02-07
申请号：US11869857
申请日：2007-10-10
申请人： Vladislav Vashchenko , Peter Hopper , Yuri Mirgorodski
发明人： Vladislav Vashchenko , Peter Hopper , Yuri Mirgorodski
IPC分类号： H01L21/86
CPC分类号： H01L23/367 , H01L21/84 , H01L27/0211 , H01L27/12 , H01L27/1203 , H01L27/1207 , H01L2924/0002 , H01L2924/00
摘要： In some embodiments, a chip with a metal heat flow path extending between a terminal of a transistor thereof and bulk semiconductor material of the chip (e.g., from the terminal to a substrate over which the transistor is formed or to the body of a semiconductor device adjacent to the transistor) and methods for manufacturing such a chip. The chip can be implemented by a semiconductor on insulator (SOI) process and can include at least one bipolar or MOS transistor, an insulator underlying the transistor, a semiconductor substrate underlying the insulator, and a metal heat flow path extending between a terminal of the transistor through the insulator to the substrate. Preferably, the metal heat flow path is a metal interconnect formed by a process step (or steps) of the same type performed to produce other metal interconnects of the chip. The chip can be an SOI chip including output circuitry and low-power circuitry, with at least one power transistor of the output circuitry, but no transistor of the low-power circuitry, having a terminal coupled to a metal heat flow path. Other embodiments are a chip including transistors and a feedback control loop coupled to at least one of the transistors for sensing temperature of the transistor and controlling at least one operating parameter of the transistor in response to the sensed temperature, and a method for manufacturing such chip.
摘要翻译：在一些实施例中，具有在其晶体管的端子和芯片的体半导体材料之间延伸的金属热流路的芯片（例如，从端子到其上形成晶体管的衬底或半导体器件的主体）与晶体管相邻）以及用于制造这种芯片的方法。该芯片可以通过半导体绝缘体（SOI）工艺来实现，并且可以包括至少一个双极或MOS晶体管，晶体管下面的绝缘体，绝缘体下面的半导体衬底，以及在绝缘体的端子之间延伸的金属热流路径晶体管通过绝缘体到基板。优选地，金属热流路径是通过对芯片的其他金属互连进行的相同类型的工艺步骤（或步骤）形成的金属互连。该芯片可以是包括输出电路和低功率电路的SOI芯片，其中至少一个输出电路的功率晶体管，但是没有低功率电路的晶体管具有耦合到金属热流路径的端子。其他实施例是包括晶体管和耦合到晶体管中的至少一个的反馈控制环路的芯片，用于感测晶体管的温度并且响应于感测到的温度控制晶体管的至少一个操作参数，以及用于制造这种芯片的方法。

56. 发明申请

US20060266925A1 Active pixel sensor cell with integrating varactor and method for using such cell 有权
公开(公告)号：US20060266925A1
公开(公告)日：2006-11-30
申请号：US11496951
申请日：2006-08-01
申请人： Peter Hopper , Philipp Lindorfer , Mark Poulter , Yuri Mirgorodski
发明人： Peter Hopper , Philipp Lindorfer , Mark Poulter , Yuri Mirgorodski
IPC分类号： H01L27/00
CPC分类号： H01L27/14609 , H04N5/35572 , H04N5/361 , H04N5/37452
摘要： An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

57. 发明授权

US06621736B1 Method of programming a splity-gate flash memory cell with a positive inhibiting word line voltage 有权
标题翻译：用正禁止字线电压编程分闸器闪存单元的方法
公开(公告)号：US06621736B1
公开(公告)日：2003-09-16
申请号：US10091927
申请日：2002-03-05
申请人： Yuri Mirgorodski , Pavel Poplevine , Mark W. Poulter
发明人： Yuri Mirgorodski , Pavel Poplevine , Mark W. Poulter
IPC分类号： G11C1604
CPC分类号： G11C16/0425 , G11C16/12
摘要： A split-gate flash memory array is programmed, in part, by applying a programming voltage to the row of cells that include the to-be-programmed cells, and an inhibiting voltage to the row of cells that share the same source line as the row that includes the to-be-programmed cells. The inhibiting voltage is greater than zero and less than the programming voltage.
摘要翻译：分割栅极闪存阵列部分地通过将编程电压施加到包括待编程单元的单元行，以及与该单元阵列共享相同源极线的抑制电压来编程包括要编程的单元格的行。抑制电压大于零，小于编程电压。

58. 发明授权

US08183621B2 Non-volatile memory cell having a heating element and a substrate-based control gate 有权
标题翻译：具有加热元件和基于基板的控制栅极的非易失性存储单元
公开(公告)号：US08183621B2
公开(公告)日：2012-05-22
申请号：US13037199
申请日：2011-02-28
申请人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
发明人： Jeffrey A. Babcock , Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11558 , H01L29/66825 , H01L29/7841 , H01L29/7881
摘要： The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
摘要翻译：可以通过利用局部加热元件来使得非易失性存储器（NVM）被编程和擦除的次数大大增加，所述局部加热元件在NVM被编程和擦除时使隧道电荷载体损坏的氧化物退火。在编程和擦除之前，加热元件的热量时，编程和擦除电压也会降低。

59. 发明申请

US20110233670A1 METHOD OF FORMING A REGION OF GRADED DOPING CONCENTRATION IN A SEMICONDUCTOR DEVICE AND RELATED APPARATUS 有权
标题翻译：形成半导体器件中的分级掺杂浓度区域的方法及相关装置
公开(公告)号：US20110233670A1
公开(公告)日：2011-09-29
申请号：US13156184
申请日：2011-06-08
申请人： William French , Erika Mazotti , Yuri Mirgorodski
发明人： William French , Erika Mazotti , Yuri Mirgorodski
IPC分类号： H01L29/78
CPC分类号： H01L29/0847 , H01L21/2253 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/7835
摘要： A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile.
摘要翻译：用于形成半导体器件的掺杂区域的方法包括用掩模掩蔽衬底的一部分。掩模被配置为在掺杂区域内产生渐变掺杂分布。该方法还包括使用掩模执行植入物以在衬底中产生掺杂区域和未掺杂区域。该方法还包括扩散掺杂区域以在掺杂区域中产生渐变掺杂分布。掩模可以包括具有分布在整个光致抗蚀剂材料中的开口的第一区域，其中开口的尺寸和间隔变化。掩模还可以包括具有分布在整个开放区域中的光致抗蚀剂材料块的第二区域，其中光刻胶块的尺寸和间距变化。扩散掺杂区域可以包括施加高温退火以使掺杂和未掺杂区域平滑以产生线性渐变的掺杂分布。

60. 发明授权

US07919805B1 Non-volatile memory cell with two capacitors and one PNP transistor and a method of forming such a cell in a 1-poly SOI technology 有权
标题翻译：具有两个电容器和一个PNP晶体管的非易失性存储器单元以及在1-poly SOI技术中形成这样的单元的方法
公开(公告)号：US07919805B1
公开(公告)日：2011-04-05
申请号：US11807322
申请日：2007-05-25
申请人： Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
发明人： Yuri Mirgorodski , Natalia Lavrovskaya , Saurabh Desai
IPC分类号： H01L29/76
CPC分类号： H01L27/11558 , G11C16/0416 , G11C2216/04 , G11C2216/10 , H01L27/11519
摘要： In a non-volatile memory cell, a single poly SOI technology is used to save space and achieve low current programming by providing two capacitors formed in an n-material over an NBL, forming a inverter in an n-material over a PBL, and isolating the NBL from the PBL by means of a lightly doped region or a deep trench isolation region.
摘要翻译：在非易失性存储单元中，使用单个多晶硅技术来节省空间并通过在NBL上形成在n材料中形成的两个电容器来形成低电流编程，从而在PBL上形成n材料中的逆变器，以及通过轻掺杂区域或深沟槽隔离区域将PBL与PBL隔离。

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