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    • 1. 发明申请
    • Active pixel sensor cell with integrating varactor and method for using such cell
    • 具有积分变容二极管的有源像素传感器单元和使用这种单元的方法
    • US20050269482A1
    • 2005-12-08
    • US10863058
    • 2004-06-08
    • Peter HopperPhilipp LindorferMark PoulterYuri Mirgorodski
    • Peter HopperPhilipp LindorferMark PoulterYuri Mirgorodski
    • H01L27/146H04N5/353H04N5/361H04N5/3745H01L27/00
    • H01L27/14609H04N5/35572H04N5/361H04N5/37452
    • An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
    • 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管,用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间,可以将光电二极管暴露于​​光子,以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间,每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管,每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言,其中曝光电荷指示所有次曝光电荷的总和。
    • 4. 发明授权
    • Active pixel sensor cell with integrating varactor and method for using such cell
    • 具有积分变容二极管的有源像素传感器单元和使用这种单元的方法
    • US07262401B2
    • 2007-08-28
    • US11496951
    • 2006-08-01
    • Peter J. HopperPhilipp LindorferMark W. PoulterYuri Mirgorodski
    • Peter J. HopperPhilipp LindorferMark W. PoulterYuri Mirgorodski
    • H01L27/00H04N3/14
    • H01L27/14609H04N5/35572H04N5/361H04N5/37452
    • An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
    • 包括至少一个光电二极管和复位电路的有源像素传感器单元和耦合到光电二极管的积分变容二极管,用于读出这样的单元的方法以及包括这种单元阵列的图像传感器。 在曝光间隔期间,可以将光电二极管暴露于​​光子,以在光电二极管的第一节点处累积次曝光电荷序列。 在曝光间隔的不同子曝光间隔期间,每个次曝光电荷在第一节点处累积。 在每个复位间隔的每一个期间复位光电二极管,每个复位间隔发生在不同的次曝光间隔之前。 指示在曝光间隔期间在存储节点处累积的曝光电荷的输出信号可以从单元断言,其中曝光电荷指示所有次曝光电荷的总和。
    • 5. 发明授权
    • Apparatus and method for storing analog information in EEPROM memory
    • 用于将模拟信息存储在EEPROM存储器中的装置和方法
    • US07233521B1
    • 2007-06-19
    • US11078761
    • 2005-03-11
    • Yuri MirgorodskiPeter J. HopperVladislav VashshencoPhilipp Lindorfer
    • Yuri MirgorodskiPeter J. HopperVladislav VashshencoPhilipp Lindorfer
    • G11C11/34
    • G11C27/005G11C11/5621G11C16/0441G11C16/10
    • A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.
    • 一种能够接收模拟信号并将其存储为数字信号的存储装置。 存储装置包括被配置为接收模拟输入电压的输入节点和两个非易失性存储单元。 第二非易失性存储单元被耦合以从输入节点接收模拟输入信号。 第二非易失性存储单元能够被编程为多个编程状态之一。 耦合到第二非易失性存储单元的第一非易失性存储单元也能够被编程为多个编程状态之一。 在操作期间,第二非易失性存储器单元和第一非易失性存储器单元都被编程为指示模拟输入电压的大小的选择的第二编程状态。 第一编程状态和第二编程状态一起表示与模拟输入电压的大小相称的数字值。
    • 7. 发明授权
    • NVM PMOS-cell with one erased and two programmed states
    • NVM PMOS单元具有一个擦除和两个编程状态
    • US07113427B1
    • 2006-09-26
    • US11076711
    • 2005-03-09
    • Yuri MirgorodskiPeter J. HopperVladislav VashchenkoPhilipp Lindorfer
    • Yuri MirgorodskiPeter J. HopperVladislav VashchenkoPhilipp Lindorfer
    • G11C16/04
    • G11C11/5628G11C16/12G11C16/3459H01L27/115H01L29/7881
    • NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
    • 用于存储三个电荷电平的NVM单元:一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构,一个实施例组合了具有不同阈值电压的两个并联晶体管,另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压,使第一个编程区中的栅极电压升高,然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压,将栅极电压升高到第一编程区并进入第二编程区,然后将其向下斜坡。 可以选择先将电压降低,然后关闭通道上的电压。