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51. 发明申请

US20050235240A1 Method for reducing layers revision in engineering change order 有权
标题翻译：减少工程变更订单中层次修订的方法
公开(公告)号：US20050235240A1
公开(公告)日：2005-10-20
申请号：US10826560
申请日：2004-04-16
申请人： Li-Chun Tien
发明人： Li-Chun Tien
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5068
摘要： An engineering change order (ECO) base cell module is disclosed along with some of its applications. The cell has an N well and P well, P+ implant and N+ implant regions, N well pick-up and P well pick-up regions, a first power supply line, and a second power supply line, wherein the ECO base cell has a same configuration as a standard logic cell and is alterable in at least one metal layer for making one or more connections to form a functional logic cell.
摘要翻译：公开了工程变更订单（ECO）基本单元模块及其一些应用程序。电池具有N阱和P阱，P +注入和N +注入区，N阱拾取和P阱拾取区，第一电源线和第二电源线，其中ECO基电池具有与标准逻辑单元相同的配置，并且在至少一个金属层中是可变的，用于使一个或多个连接形成功能逻辑单元。

52. 发明授权

US06903389B1 Variable layout design for multiple voltage applications 有权
标题翻译：多电压应用的可变布局设计
公开(公告)号：US06903389B1
公开(公告)日：2005-06-07
申请号：US10868606
申请日：2004-06-15
申请人： Chun-Hui Tai , Li-Chun Tien
发明人： Chun-Hui Tai , Li-Chun Tien
IPC分类号： H01L27/02 , H01L27/10 , H01L27/118
CPC分类号： H01L27/11807 , H01L27/0207
摘要： An integrated circuit it comprises a logic cell. The logic cell is without nwell contacts and comprises top and bottom voltage supply wires. The integrated circuit also comprises a first filler cell comprising top and d bottom voltage supply wires and an nwell region coupled to the bottom voltage supply wire. The integrated circuit further comprises a second filler cell with an nwell region coupled to a top voltage supply wire. The integrated circuit still further comprises a third filler cell comprising top and bottom voltage supply wires. The third filler cell also comprising a pair of nwell regions. One of nwell regions is coupled to the top voltage supply wire and the other nwell region is coupled to the bottom voltage supply wire. The standard cell and the filler cells each comprise a PRboundary overlapping a top portion of the nwell region in each cell by a first distance.
摘要翻译：其集成电路包括逻辑单元。逻辑单元没有nwell触点，并且包括顶部和底部电压电源线。集成电路还包括第一填充单元，其包括顶部和底部电压电源线以及耦合到底部电压电源线的nwell区域。集成电路还包括具有耦合到顶部电压电源线的nwell区域的第二填充单元。集成电路还包括包括顶部和底部电压电源线的第三填充单元。第三填充单元还包括一对nwell区域。 n个区域中的一个耦合到顶部电压电源线，另一个nwell区域耦合到底部电压电源线。标准单元和填充单元每个都包括与每个单元格中的nwell区域的顶部重叠第一距离的PR边界。

53. 发明授权

US09323881B2 Method and layout of an integrated circuit 有权
标题翻译：集成电路的方法和布局
公开(公告)号：US09323881B2
公开(公告)日：2016-04-26
申请号：US14341130
申请日：2014-07-25
申请人： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Ruei-Wun Sun , Hung-Jung Tseng , Shun Li Chen , Li-Chun Tien
发明人： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Ruei-Wun Sun , Hung-Jung Tseng , Shun Li Chen , Li-Chun Tien
IPC分类号： G06F17/50 , H01L23/482
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5072 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.
摘要翻译：集成电路布局包括P型有源区和N型有源区，以及多个树干。集成电路布局还包括连接到P型有源区的第一金属连接; 以及连接到N型有源区的第二金属连接。多个树干的每个中继线与第一金属连接和第二金属连接电连接。多个树干的每个树干基本上垂直于第一金属连接和第二金属连接。多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度。

54. 发明授权

US08816403B2 Efficient semiconductor device cell layout utilizing underlying local connective features 有权
标题翻译：利用潜在的本地连接特征的高效半导体器件单元布局
公开(公告)号：US08816403B2
公开(公告)日：2014-08-26
申请号：US13238294
申请日：2011-09-21
申请人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
发明人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
IPC分类号： H01L27/118 , H01L23/522
CPC分类号： H01L27/0207 , H01L2027/11859
摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.
摘要翻译：提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。器件单元可以是整个集成电路中使用的重复单元。布局样式利用多晶硅级别的无多晶硅的区域，并且可以容纳其中或其中的导电引线。导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。下面的局部导电引线可以形成下面的信号线，允许额外的功率网线包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

55. 发明授权

US08482990B2 Memory edge cell 有权
标题翻译：内存边缘单元格
公开(公告)号：US08482990B2
公开(公告)日：2013-07-09
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译：电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

56. 发明申请

US20120286341A1 Adding Decoupling Function for TAP Cells 有权
标题翻译：添加TAP单元的去耦功能
公开(公告)号：US20120286341A1
公开(公告)日：2012-11-15
申请号：US13106521
申请日：2011-05-12
申请人： Kuo-Ji Chen , Li-Chun Tien
发明人： Kuo-Ji Chen , Li-Chun Tien
IPC分类号： H01L29/94
CPC分类号： H01L29/94 , H01L23/528 , H01L27/0805 , H01L27/0808 , H01L29/107 , H01L29/1095 , H01L2924/0002 , H01L2924/00
摘要： A tap cell includes a well region and a well pickup region on the well region; a VDD power rail; and a VSS power rail. A MOS capacitor includes a gate electrode line acting as a first capacitor plate, and the well pickup region acting as a part of a second capacitor plate. A first one of the first and second capacitor plates is coupled to the VDD power rail, and a second one of the first and second capacitor plates is coupled to the VSS power rail.
摘要翻译：抽头单元包括阱区域和阱区域上的阱拾取区域; 一个VDD电源轨; 和VSS电源轨。 MOS电容器包括用作第一电容器板的栅极电极线和用作第二电容器板的一部分的阱拾取区域。第一和第二电容器板中的第一电容器板耦合到VDD电源轨，并且第一和第二电容器板中的第二个耦合到VSS电源轨。

57. 发明申请

US20070284618A1 Transistor layout for standard cell with optimized mechanical stress effect 有权
标题翻译：具有优化机械应力效应的标准电池的晶体管布局
公开(公告)号：US20070284618A1
公开(公告)日：2007-12-13
申请号：US11441557
申请日：2006-05-26
申请人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
发明人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
IPC分类号： H01L27/10 , H01L29/739
CPC分类号： H01L27/0207 , H01L27/11803 , H01L29/7849
摘要： A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.
摘要翻译：公开了一种用于标准单元中晶体管的布局。晶体管的布局包括有源区，其中至少一个部分具有第一边缘，并且至少一个部分具有全部垂直于该晶体管的沟道的第二边缘; 并且放置在有源区域的顶部上的栅极与栅极的边缘到第一边缘的距离短于距栅极的边缘到有源区域的第二边缘的距离，其中有源区域为非矩形。

58. 发明申请

US20050086629A1 Method of defining forbidden pitches for a lithography exposure tool 失效
公开(公告)号：US20050086629A1
公开(公告)日：2005-04-21
申请号：US10688500
申请日：2003-10-17
申请人： Jaw-Jung Shin , Chun-Kuang Chen , Tsai-Sheng Gau , Burn-Jeng Lin , Li-Chun Tien , Mi-Chang Chang , Yu-Jun Chou , Jan-Wen You , King-Chang Shu , Li-Jui Chen
发明人： Jaw-Jung Shin , Chun-Kuang Chen , Tsai-Sheng Gau , Burn-Jeng Lin , Li-Chun Tien , Mi-Chang Chang , Yu-Jun Chou , Jan-Wen You , King-Chang Shu , Li-Jui Chen
IPC分类号： G03F1/14 , G03F7/20 , G06F17/50
CPC分类号： G03F7/70641 , G03F1/44 , G03F7/70425 , G03F7/70433 , G03F7/705
摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

59. 发明授权

US08819610B2 Method and layout of an integrated circuit 有权
标题翻译：集成电路的方法和布局
公开(公告)号：US08819610B2
公开(公告)日：2014-08-26
申请号：US13778912
申请日：2013-02-27
申请人： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Ruei-Wun Sun , Hung-Jung Tseng , Shun Li Chen , Li-Chun Tien
发明人： Hsiang-Jen Tseng , Ting-Wei Chiang , Wei-Yu Chen , Ruei-Wun Sun , Hung-Jung Tseng , Shun Li Chen , Li-Chun Tien
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5072 , H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks.
摘要翻译：集成电路布局包括P型有源区，N型有源区，第一金属连接，第二金属连接和多个树干。多个树干基本并排地形成并且彼此平行。第一金属连接基本上设置在P型有源区上，并且与P型有源区中的PMOS晶体管的漏极区域电连接。第二金属连接基本上设置在N型有源区上，并且与N型有源区中的NMOS晶体管的漏区电连接。多个树干电连接并且基本上垂直于第一金属连接和第二金属连接。多个树干的第一树干具有比多个树干中的其他树干的宽度宽的宽度，并且布置成位于两组树干之间。

60. 发明授权

US08455354B2 Layouts of POLY cut openings overlapping active regions 有权
标题翻译： POLY切割开口与活跃区域重叠的布局
公开(公告)号：US08455354B2
公开(公告)日：2013-06-04
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

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