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1. 发明授权

US07321139B2 Transistor layout for standard cell with optimized mechanical stress effect 有权
标题翻译：具有优化机械应力效应的标准电池的晶体管布局
公开(公告)号：US07321139B2
公开(公告)日：2008-01-22
申请号：US11441557
申请日：2006-05-26
申请人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
发明人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
IPC分类号： H01L27/10 , H01L29/739 , H01L29/73 , H01L29/74 , H01L31/062
CPC分类号： H01L27/0207 , H01L27/11803 , H01L29/7849
摘要： A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.
摘要翻译：公开了一种用于标准单元中晶体管的布局。晶体管的布局包括有源区，其中至少一个部分具有第一边缘，并且至少一个部分具有全部垂直于晶体管的沟道的第二边缘; 并且放置在有源区域的顶部上的栅极与栅极的边缘到第一边缘的距离短于距栅极的边缘到有源区域的第二边缘的距离，其中有源区域为非矩形。

2. 发明申请

US20070284618A1 Transistor layout for standard cell with optimized mechanical stress effect 有权
标题翻译：具有优化机械应力效应的标准电池的晶体管布局
公开(公告)号：US20070284618A1
公开(公告)日：2007-12-13
申请号：US11441557
申请日：2006-05-26
申请人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
发明人： Mi-Chang Chang , Liang-Kai Han , Huan-Tsung Huang , Wen-Jya Liang , Li-Chun Tien
IPC分类号： H01L27/10 , H01L29/739
CPC分类号： H01L27/0207 , H01L27/11803 , H01L29/7849
摘要： A layout for a transistor in a standard cell is disclosed. The layout for a transistor comprises an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.
摘要翻译：公开了一种用于标准单元中晶体管的布局。晶体管的布局包括有源区，其中至少一个部分具有第一边缘，并且至少一个部分具有全部垂直于该晶体管的沟道的第二边缘; 并且放置在有源区域的顶部上的栅极与栅极的边缘到第一边缘的距离短于距栅极的边缘到有源区域的第二边缘的距离，其中有源区域为非矩形。

3. 发明授权

US06602749B2 Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance 有权
公开(公告)号：US06602749B2
公开(公告)日：2003-08-05
申请号：US09955461
申请日：2001-09-17
申请人： Kuo-Chi Tu , Wen-Jya Liang
发明人： Kuo-Chi Tu , Wen-Jya Liang
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811
摘要： Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain regions a bitline stud layer separated from and rising above the storage capacitor. Within the memory cell structure, and at a minimum storage capacitor to bitline stud layer separation, a capacitor plate layer is further separated from the bitline stud layer than a capacitor node layer.

4. 发明授权

US06249018B1 Fabrication method to approach the conducting structure of a DRAM cell with straightforward bit line 有权
标题翻译：用直接位线接近DRAM单元的导电结构的制造方法
公开(公告)号：US06249018B1
公开(公告)日：2001-06-19
申请号：US09292128
申请日：1999-04-14
申请人： Ing-Ruey Liaw , Wen-Jya Liang
发明人： Ing-Ruey Liaw , Wen-Jya Liang
IPC分类号： H01L2994
CPC分类号： H01L27/10888 , H01L27/10808 , Y10S257/908
摘要： A conducting structure of a COB cell of DRAM includes an piecewise straight active area and substantially straight bitline formed over a semiconductor substrate upon which a first dielectric layer existed. Contact holes are formed over the piecewise straight active area for electrically exposing both nodes (source and drain), of the active area of the access device. An offset landing plug pattern is defined by a photoresist-clear pattern beside, say, the source node of the primary contact pattern and recess-etched into the first dielectric layer and electrically connected to the source node of the primary contact structure finally. The contact structure is then formed by a deposition-etched process, which performs as a landing plug for contact of the upper contact structures. The top area of the landing plug is defined through the additive pattern of the primary contact as well as the offset landing plug pattern. Thereafter, a second dielectric layer is deposited on the first dielectric layer and the contact structure. A bit line contact is then formed in the second dielectric layer and defined at the offset position of the source node of the landing plug contact structure and electrically connected with it, so as to provide a capability of forming a substantially straight bit line lies on an off-axis site to the piecewise straight active area and the primary substrate contact plug.
摘要翻译： DRAM的COB单元的导电结构包括在其上存在第一介电层的半导体衬底上形成的分段直的有源区和基本上直的位线。在分段直线有效区域上形成接触孔，以电接触接入设备的有效区域的两个节点（源极和漏极）。偏移着陆塞图案由除了主接触图案的源节点旁边的光致抗蚀剂透明图案限定，并且凹入蚀刻到第一介电层中，并最终电连接到主接触结构的源节点。然后通过沉积蚀刻工艺形成接触结构，其作为用于上部接触结构的接触的着陆塞。着陆塞的顶部区域通过主接触的附加图案以及偏移着陆塞图案来定义。此后，在第一电介质层和接触结构上沉积第二电介质层。然后，在第二电介质层中形成位线接触并限定在着陆插头接触结构的源节点的偏移位置处并与其电连接，以便提供形成基本上直的位线的能力，位于离轴位置到分段直线有源区域和主基板接触插塞。

5. 发明授权

US5780339A Method for fabricating a semiconductor memory cell in a DRAM 失效
标题翻译：在DRAM中制造半导体存储单元的方法
公开(公告)号：US5780339A
公开(公告)日：1998-07-14
申请号：US850908
申请日：1997-05-02
申请人： Bin Liu , Wen-Jya Liang , Yeh-Sen Lin
发明人： Bin Liu , Wen-Jya Liang , Yeh-Sen Lin
IPC分类号： H01L21/8242
CPC分类号： H01L27/10852
摘要： This present invention is a method of fabricating a semiconductor memory cell in a DRAM. This invention utilizes a inter plug technique and nitride sidewall spacers to improve deep node contact etching damage and reduce the number of mask steps for typical landing pad processes. Thus, the method of this invention allows the manufacture of a semiconductor memory cell that reduces the difficulties due to the high aspect ratio of the contact hole of a storage node.
摘要翻译：本发明是一种在DRAM中制造半导体存储单元的方法。本发明利用插塞技术和氮化物侧壁间隔物来改善深层接触蚀刻损伤并减少典型的着陆焊盘工艺的掩模步骤的数量。因此，本发明的方法允许制造半导体存储单元，其减少由于存储节点的接触孔的高纵横比引起的困难。

6. 发明授权

US08125028B2 Semiconductor devices for high power application 有权
标题翻译：用于高功率应用的半导体器件
公开(公告)号：US08125028B2
公开(公告)日：2012-02-28
申请号：US12265580
申请日：2008-11-05
申请人： Hung-Shern Tsai , Geeng-Lih Lin , Wen-Jya Liang
发明人： Hung-Shern Tsai , Geeng-Lih Lin , Wen-Jya Liang
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/7809
摘要： Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.
摘要翻译：介绍了高压应用的半导体器件。大功率半导体器件包括第一类掺杂半导体衬底和沉积在其上的第二类掺杂外延层。第一类掺杂体区设置在第二类型掺杂外延层中。在第二类型掺杂外延层中形成重掺杂漏极区，并与具有隔离区和沟道的第一类型掺杂体区隔离。第二种深度重掺杂区域从重掺杂漏极区延伸到半导体衬底。一对反相型重掺杂源极区域设置在第一掺杂体区域中。栅电极设置在通道上方，介于其间的电介质层。高功率半导体器件与具有第一类型深度重掺杂区域的其它半导体器件隔离。

7. 发明申请

US20090261409A1 SEMICONDUCTOR DEVICES FOR HIGH POWER APPLICATION 有权
标题翻译：用于高功率应用的半导体器件
公开(公告)号：US20090261409A1
公开(公告)日：2009-10-22
申请号：US12265580
申请日：2008-11-05
申请人： Hung-Shern Tsai , Geeng-Lih Lin , Wen-Jya Liang
发明人： Hung-Shern Tsai , Geeng-Lih Lin , Wen-Jya Liang
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/7809
摘要： Semiconductor devices for high voltage application are presented. A high power semiconductor device includes a first type doped semiconductor substrate and a second type doped epitaxial layer deposited thereon. A first type doped body region is disposed in the second type doped epitaxial layer. A heavily doped drain region is formed in the second type doped epitaxial layer and isolated from the first type doped body region with an isolation region and a channel. A second type deep heavily doped region extends from the heavily doped drain region to the semiconductor substrate. A pair of inversed type heavily doped source regions is disposed in the first type doped body region. A gate electrode is disposed overlying the channel with a dielectric layer interposed therebetween. The high power semiconductor device is isolated from the other semiconductor devices with a first type deep heavily doped region.
摘要翻译：介绍了高压应用的半导体器件。大功率半导体器件包括第一类掺杂半导体衬底和沉积在其上的第二类掺杂外延层。第一类掺杂体区设置在第二类型掺杂外延层中。在第二类型掺杂外延层中形成重掺杂漏极区，并与具有隔离区和沟道的第一类型掺杂体区隔离。第二种深度重掺杂区域从重掺杂漏极区延伸到半导体衬底。一对反相型重掺杂源极区域设置在第一掺杂体区域中。栅电极设置在通道上方，介于其间的电介质层。高功率半导体器件与具有第一类型深度重掺杂区域的其它半导体器件隔离。

8. 发明授权

US06277709B1 Method of forming shallow trench isolation structure 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US06277709B1
公开(公告)日：2001-08-21
申请号：US09628214
申请日：2000-07-28
申请人： Yin-Pin Wang , Chung-Ju Lee , Wen-Jya Liang , Jhy-Weei Hsia , Fu-Liang Yang , Yuh-Sheng Chern
发明人： Yin-Pin Wang , Chung-Ju Lee , Wen-Jya Liang , Jhy-Weei Hsia , Fu-Liang Yang , Yuh-Sheng Chern
IPC分类号： H01L2176
CPC分类号： H01L21/763 , H01L21/76224
摘要： A method for manufacturing a shallow trench isolation structure. A pad oxide layer and a mask layer are formed over a substrate. Portions of the mask layer, the pad layer and substrate are removed forming a trench. Oxidation of the substrate within the trench forms a linear oxide layer. The substrate at the bottom of the trench is exposed by removing a portion of the linear oxide layer at the bottom of the trench. A polysilicon layer, deposited completely over the mask, fills the trench as well. The polysilicon layer on the mask layer and outside the trench is removed, leaving polysilicon within the trench, which forms a polysilicon plug. A thin conformal barrier layer is formed over the substrate. An insulator layer is deposited above the barrier layer. The isolation layer and barrier layer on top of the mask as well as outside the trench are removed using a chemical mechanical polishing method. The mask is removed.
摘要翻译：一种用于制造浅沟槽隔离结构的方法。在衬底上形成衬垫氧化物层和掩模层。除去掩模层，焊盘层和衬底的部分，形成沟槽。沟槽内的衬底的氧化形成线性氧化物层。通过去除沟槽底部的线性氧化物层的一部分来暴露沟槽底部的衬底。完全沉积在掩模上的多晶硅层也填充沟槽。去除掩模层和沟槽外部的多晶硅层，留下沟槽内的多晶硅，形成多晶硅塞。在衬底上形成薄的共形阻挡层。绝缘体层沉积在阻挡层上方。使用化学机械抛光方法除去掩模顶部以及沟槽外部的隔离层和阻挡层。去除面具。

9. 发明授权

US5807782A Method of manufacturing a stacked capacitor having a fin-shaped storage electrode on a dynamic random access memory cell 失效
标题翻译：制造在动态随机存取存储单元上具有鳍状存储电极的层叠电容器的方法
公开(公告)号：US5807782A
公开(公告)日：1998-09-15
申请号：US533566
申请日：1995-09-25
申请人： Chao-Ming Koh , Wen-Jya Liang , Bin Liu
发明人： Chao-Ming Koh , Wen-Jya Liang , Bin Liu
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , H01L28/88
摘要： A method for manufacturing a stacked capacitor having fin-shaped electrodes with increased capacitance on a dynamic random access memory (DRAM) cell, was achieved. The invention eliminates the need for a silicon nitride etch stop layer, which is known to cause stress in the substrate and lead to defects. The capacitor bottom electrodes having fin shaped portions is fabricated by depositing a multilayer of alternate layers of silicon oxide and doped polysilicon on a partially completed DRAM device having FETs. After forming, with single masking step, the node contacts to the substrate in the multilayer and depositing another doped polysilicon layer, the polysilicon layers and oxide layer are patterned to form the electrodes. An important feature of this invention is that the patterned multilayer is etched to the silicon oxide layer over the bottom polysilicon layer and then the silicon oxide layer(s) are isotropically etched (e.g. in HF) to form the fin capacitor. The fin structure is then used as a mask to anisotropically etch the bottom polysilicon layer, and thereby complete and electrically isolate the bottom fin-shaped electrodes. The capacitor is completed by forming the inter-electrode dielectric and depositing a top electrode layer.
摘要翻译：实现了在动态随机存取存储器（DRAM）单元上制造具有增加电容的鳍状电极的堆叠电容器的方法。本发明消除了氮化硅蚀刻停止层的需要，其已知会在衬底中引起应力并导致缺陷。具有鳍形部分的电容器底部电极通过在具有FET的部分完成的DRAM器件上沉积多层氧化硅和掺杂多晶硅的交替层来制造。在形成之后，通过单个掩模步骤，节点接触多层中的衬底并沉积另一个掺杂多晶硅层，对多晶硅层和氧化物层进行构图以形成电极。本发明的一个重要特征是，图案化多层被蚀刻到底部多晶硅层上的氧化硅层上，然后氧化硅层被各向同性地蚀刻（例如在HF中）以形成散热片电容器。然后将鳍结构用作掩模以各向异性蚀刻底部多晶硅层，从而完成并电隔离底部鳍状电极。通过形成电极间电介质并沉积顶部电极层来完成电容器。

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