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1. 发明申请

US20130069236A1 EFFICIENT SEMICONDUCTOR DEVICE CELL LAYOUT UTILIZING UNDERLYING LOCAL CONNECTIVE FEATURES 有权
标题翻译：有效的半导体器件细胞布局利用本地连接特性
公开(公告)号：US20130069236A1
公开(公告)日：2013-03-21
申请号：US13238294
申请日：2011-09-21
申请人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
发明人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
IPC分类号： H01L23/52 , G06F17/50
CPC分类号： H01L27/0207 , H01L2027/11859
摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.
摘要翻译：提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。器件单元可以是整个集成电路中使用的重复单元。布局样式利用多晶硅级别的无多晶硅的区域，并且其可以容纳其中或其中的导电引线。导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。下面的局部导电引线可以形成下面的信号线，允许额外的功率网线被包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

2. 发明授权

US08816403B2 Efficient semiconductor device cell layout utilizing underlying local connective features 有权
标题翻译：利用潜在的本地连接特征的高效半导体器件单元布局
公开(公告)号：US08816403B2
公开(公告)日：2014-08-26
申请号：US13238294
申请日：2011-09-21
申请人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
发明人： Jung-Hsuan Chen , May Chang , Chiting Cheng , Li-Chun Tien
IPC分类号： H01L27/118 , H01L23/522
CPC分类号： H01L27/0207 , H01L2027/11859
摘要： Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.
摘要翻译：提供半导体器件单元，用于形成半导体器件单元的方法和用于半导体器件单元的布局样式。器件单元可以是整个集成电路中使用的重复单元。布局样式利用多晶硅级别的无多晶硅的区域，并且可以容纳其中或其中的导电引线。导电引线由通常用于触点或通孔的材料形成，并且设置在将器件单元彼此耦合的第一金属互连级之下。下面的局部导电引线可以形成下面的信号线，允许额外的功率网线包括在可以容纳在器件单元内并根据金属轨道设计间隔规则的有限数量的金属轨道内。

3. 发明授权

US08837250B2 Method and apparatus for word line decoder layout 有权
标题翻译：字线解码器布局的方法和装置
公开(公告)号：US08837250B2
公开(公告)日：2014-09-16
申请号：US12839490
申请日：2010-07-20
申请人： You-Cheng Xiao , Hong-Chen Cheng , Chung-Ji Lu , Cheng Hung Lee , Jung-Hsuan Chen , Li-Chun Tien
发明人： You-Cheng Xiao , Hong-Chen Cheng , Chung-Ji Lu , Cheng Hung Lee , Jung-Hsuan Chen , Li-Chun Tien
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C11/413
摘要： A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.
摘要翻译：字线解码器包括多个驱动器电路，设置在驱动器电路的各个输出处的多个字线以及耦合到驱动器电路并沿第一方向取向的多个主输入线。字线解码器还包括耦合到驱动器电路并沿第一方向定向的多个次级输入线。字线解码器还包括耦合到每个主输入线的本地解码线。字线解码器还包括耦合到本地解码线并沿第一方向定向的解码线。集群解码线耦合到解码线。字线解码器被配置为基于由群集解码线和辅助输入线提供的信号来选择至少一个字线。

4. 发明授权

US08610236B2 Edge devices layout for improved performance 有权
标题翻译：边缘设备布局，以提高性能
公开(公告)号：US08610236B2
公开(公告)日：2013-12-17
申请号：US12851702
申请日：2010-08-06
申请人： Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Hung-Jen Liao , Li-Chun Tien
发明人： Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Hung-Jen Liao , Li-Chun Tien
IPC分类号： H01L27/08
CPC分类号： H01L21/28008 , H01L21/28123 , H01L21/823425 , H01L21/823481 , H01L27/0207 , H01L29/66628 , H01L29/7848
摘要： A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.
摘要翻译：字线驱动器包括具有沿半导体衬底的第一方向延伸的长度的有源区。多个指状物形成在有源区域的上表面上。多个指状物中的每一个具有在第二方向上延伸的长度，并且形成具有有效区域的一部分的MOS晶体管。第一虚设结构设置在多个指状物的外部之一和半导体衬底的边缘之间。第一虚拟结构包括至少部分地设置在有效区域的一部分上的部分。

5. 发明申请

US20120181707A1 Distributed Metal Routing 有权
标题翻译：分布式金属路由
公开(公告)号：US20120181707A1
公开(公告)日：2012-07-19
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/48 , H01L21/28
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

6. 发明授权

US08482990B2 Memory edge cell 有权
标题翻译：内存边缘单元格
公开(公告)号：US08482990B2
公开(公告)日：2013-07-09
申请号：US13025872
申请日：2011-02-11
申请人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
发明人： Hong-Chen Cheng , Ming-Yi Lee , Kuo-Hua Pan , Jung-Hsuan Chen , Li-Chun Tien , Cheng Hung Lee , Hung-Jen Liao
IPC分类号： G11C7/10
CPC分类号： G11C5/06 , G11C5/147 , G11C5/148 , G11C11/417
摘要： A circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The PMOS transistors and the NMOS transistors are configured to provide a first voltage reference node having a first reference voltage and a second voltage reference node having a second reference voltage. The first reference voltage and the second reference voltage serve as a first reference voltage and a second reference voltage for a memory cell, respectively.
摘要翻译：电路包括第一PMOS晶体管，第二PMOS晶体管，第一NMOS晶体管，第二NMOS晶体管，第三NMOS晶体管和第四NMOS晶体管。 PMOS晶体管和NMOS晶体管被配置为提供具有第一参考电压的第一电压参考节点和具有第二参考电压的第二参考电压节点。第一参考电压和第二参考电压分别用作存储器单元的第一参考电压和第二参考电压。

7. 发明授权

US08455354B2 Layouts of POLY cut openings overlapping active regions 有权
标题翻译： POLY切割开口与活跃区域重叠的布局
公开(公告)号：US08455354B2
公开(公告)日：2013-06-04
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

8. 发明授权

US09041069B2 Distributed metal routing 有权
标题翻译：分布式金属布线
公开(公告)号：US09041069B2
公开(公告)日：2015-05-26
申请号：US13007235
申请日：2011-01-14
申请人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
发明人： You-Cheng Xiao , Yen-Huei Chen , Jung-Hsuan Chen , Shao-Yu Chou , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L23/52 , H01L23/485 , H01L23/528 , H01L23/482 , H01L23/522
CPC分类号： H01L21/76879 , H01L21/768 , H01L21/76832 , H01L23/4824 , H01L23/485 , H01L23/522 , H01L23/528 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
摘要翻译：公开了一种用于分布式金属布线的系统和方法。一个实施例包括具有覆盖在metal_0层上的metal_1层的metal_0层。金属层1包括分开的平行线，具有不同信号的线分布在metal_1层上。这样的布局减小了metal_0层内的寄生电阻，因为它减小了电流行进的距离。此外，metal_1中的分布式布局允许连接到metal_2层，而不需要通孔的锤头连接。

9. 发明申请

US20120258592A1 Layouts of POLY Cut Openings Overlapping Active Regions 有权
标题翻译： POLY切割开关重叠活动区域的布局
公开(公告)号：US20120258592A1
公开(公告)日：2012-10-11
申请号：US13081115
申请日：2011-04-06
申请人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
发明人： Jung-Hsuan Chen , Yen-Huei Chen , Li-Chun Tien , Hung-Jen Liao
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/76816
摘要： A method of forming integrated circuits includes forming a mask layer over a gate electrode line, wherein the gate electrode line is over a well region of a semiconductor substrate; forming an opening in the mask layer, wherein a portion of the gate electrode line and a well pickup region of the well region are exposed through the opening; and removing the portion of the gate electrode line through the opening.
摘要翻译：形成集成电路的方法包括在栅电极线上形成掩模层，其中栅电极线在半导体衬底的阱区之上; 在所述掩模层中形成开口，其中所述栅电极线的一部分和所述阱区的阱拾取区域通过所述开口露出; 并且通过所述开口去除所述栅电极线的所述部分。

10. 发明授权

US09608604B2 Voltage level shifter with single well voltage 有权
公开(公告)号：US09608604B2
公开(公告)日：2017-03-28
申请号：US11639006
申请日：2006-12-14
申请人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
发明人： Lee-Chung Lu , Chung-Hsing Wang , Chun-Hui Tai , Li-Chun Tien , Shun-Li Chen
IPC分类号： H03L5/00 , H03K3/356
CPC分类号： H03K3/35613
摘要： This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source, a drain and a bulk coupled to a third positive voltage power supply, an output node and the second positive voltage power supply, respectively, wherein the first and second PMOS transistors are formed in a single Nwell.

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