会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 51. 发明授权
    • Method to form damascene interconnects with sidewall passivation to protect organic dielectrics
    • 形成具有侧壁钝化的镶嵌互连以保护有机电介质的方法
    • US06358842B1
    • 2002-03-19
    • US09633770
    • 2000-08-07
    • Mei-Sheng ZhouSimon ChooiYi Xu
    • Mei-Sheng ZhouSimon ChooiYi Xu
    • H01L213205
    • H01L21/76831H01L21/31138H01L21/76808
    • A new method of forming a damascene interconnect in the manufacture of an integrated circuit device has been achieved. The damascene interconnect may be a single damascene or a dual damascene. Copper conductors are provided overlying a semiconductor substrate. A first passivation layer is provided overlying the copper conductors. A low dielectric constant layer is deposited overlying the first passivation layer. An optional capping layer is deposited overlying the low dielectric constant layer. A photoresist layer is deposited overlying the capping layer. The capping layer and the low dielectric constant layer are etched through to form via openings. The photoresist layer is simultaneously stripped away while forming a sidewall passivation layer on the sidewalls of the via openings using a sulfur-containing gas. Sidewall bowing and via poisoning are thereby prevented. The first passivation layer is etched through to expose the underlying copper conductors. A copper layer is deposited overlying the capping layer and filling the via openings. The copper layer is polished down to complete the damascene interconnects in the manufacture of the integrated circuit device.
    • 已经实现了在集成电路器件的制造中形成镶嵌互连的新方法。 镶嵌互连可以是单镶嵌或双镶嵌。 提供铜导体覆盖在半导体衬底上。 第一钝化层被提供在铜导体上。 沉积在第一钝化层上的低介电常数层。 沉积覆盖在低介电常数层上的可选的覆盖层。 沉积在覆盖层上的光致抗蚀剂层。 覆盖层和低介电常数层被蚀刻通过以形成通孔。 同时剥离光致抗蚀剂层,同时使用含硫气体在通路孔的侧壁上形成侧壁钝化层。 从而防止侧壁弯曲和通过中毒。 蚀刻第一钝化层以暴露下面的铜导体。 沉积覆盖覆盖层并填充通孔的铜层。 铜层被抛光以在集成电路器件的制造中完成镶嵌互连。
    • 52. 发明授权
    • Integration of silicon-rich material in the self-aligned via approach of dual damascene interconnects
    • 将富硅材料集成在双镶嵌互连的自对准通孔中
    • US06350675B1
    • 2002-02-26
    • US09686282
    • 2000-10-12
    • Simon ChooiMei-Sheng ZhouSubhash GuptaYi Xu
    • Simon ChooiMei-Sheng ZhouSubhash GuptaYi Xu
    • H01L214763
    • H01L21/76832H01L21/0274H01L21/31116H01L21/31144H01L21/7681H01L21/76825H01L21/76826
    • This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically, in the formation of self-aligned dual damascene interconnects and vias, which incorporates low dielectric constant intermetal dielectrics (IMD) and utilizes silylated top surface imaging (TSI) photoresist, with a single or multi-step selective reactive ion etch (RIE) process, to form trench/via opening. The invention incorporates the use of a silylated top surface imaging (TSI) resist etch barrier layer to form the via pattern, in the first level of a dual damascene process. Two variations of using the top surface imaging (TSI) resist, with and without leaving an exposed region in place, are described in the first and second embodiment of the invention, and in addition, a thin dielectric layer is made use of just below the resist layer. Provided adhesion between the top surface imaging (TSI) photoresist and the low dielectric constant intermetal dielectric (IMD) is good, the thin dielectric layer described above can be omitted, yielding the third and fourth embodiment of the invention. Special attention in the process is given to protecting the integrity of the low dielectric constant intermetal dielectric (ILD) material, selected from the group consisting of organic based or carbon doped silicon dioxide.
    • 本发明涉及用于半导体集成电路器件的制造方法,更具体地说,涉及形成自对准的双镶嵌互连和通孔,其结合了低介电常数金属间电介质(IMD)并利用甲硅烷基化的顶表面成像(TSI )光致抗蚀剂,具有单步或多步选择性反应离子蚀刻(RIE)工艺,以形成沟槽/通孔。 本发明包括在双镶嵌工艺的第一水平中使用甲硅烷基化的顶表面成像(TSI)抗蚀剂蚀刻阻挡层以形成通孔图案。 在本发明的第一和第二实施例中描述了使用顶表面成像(TSI)抗蚀剂的两种变型,其具有和不具有将暴露区域保持在适当位置,此外,使用刚好低于 抗蚀剂层。 提供顶表面成像(TSI)光致抗蚀剂和低介电常数金属间电介质(IMD)之间的粘附性是好的,可以省略上述薄介电层,产生本发明的第三和第四实施例。 该方法中特别注意保护低介电常数金属间电介质(ILD)材料的完整性,该材料选自有机基或掺碳二氧化硅。
    • 53. 发明授权
    • Damascene structure with reduced capacitance using a carbon nitride,
boron nitride, or boron carbon nitride passivation layer, etch stop
layer, and/or cap layer
    • 使用碳氮化物,氮化硼或氮化硼钝化层,蚀刻停止层和/或覆盖层的具有降低的电容的镶嵌结构
    • US06165891A
    • 2000-12-26
    • US435434
    • 1999-11-22
    • Simon ChooiYi XuMei Sheng Zhou
    • Simon ChooiYi XuMei Sheng Zhou
    • H01L21/311H01L21/318H01L21/768H01L23/522H01L23/532H01L21/4763G03C5/00H01L21/302H01L23/48
    • H01L21/76835H01L21/31122H01L21/318H01L21/76802H01L21/76807H01L21/76829H01L21/76834H01L23/5226H01L23/5329H01L2924/0002H01L2924/00
    • A method and structure for forming a damascene structure with reduced capacitance by forming one or more of: the passivation layer, the etch stop layer, and the cap layer using a low dielectric constant material comprising carbon nitride, boron nitride, or boron carbon nitride. The method begins by providing a semiconductor structure having a first conductive layer thereover. A passivation layer is formed on the first conductive layer. A first dielectric layer is formed over the passivation layer, and an etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the etch stop layer, and an optional cap layer can be formed over the second dielectric layer. The cap layer, the second dielectric layer, the etch stop layer, and the first dielectric layer are patterned to form a via opening stopping on said passivation layer and a trench opening stopping on the first conductive layer. A carbon nitride passivation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen atmosphere. A boron nitride passivation layer, etch stop layer, or cap layer can be formed by PECVD using B.sub.2 H.sub.6, ammonia, and nitrogen. A boron carbon nitride passivatation layer, etch stop layer, or cap layer can be formed by magnetron sputtering from a graphite target in a nitrogen and B.sub.2 H.sub.6 atmosphere.
    • 通过使用包含碳氮化物,氮化硼或碳氮化硼的低介电常数材料通过形成钝化层,蚀刻停止层和盖层中的一个或多个来形成具有降低的电容的镶嵌结构的方法和结构。 该方法开始于提供其上具有第一导电层的半导体结构。 在第一导电层上形成钝化层。 第一电介质层形成在钝化层之上,并且在第一介电层上形成蚀刻停止层。 第二介电层形成在蚀刻停止层上方,并且可以在第二介电层上形成任选的盖层。 图案化盖层,第二电介质层,蚀刻停止层和第一介电层,以形成在所述钝化层上停止的通孔开口和在第一导电层上停止的沟槽开口。 碳氮化物钝化层,蚀刻停止层或盖层可以通过在氮气气氛中的石墨靶磁控溅射来形成。 可以通过使用B2H6,氨和氮的PECVD形成氮化硼钝化层,蚀刻停止层或盖层。 硼氮化物钝化层,蚀刻停止层或盖层可以通过在氮气和B2H6气氛中的石墨靶的磁控溅射形成。
    • 54. 发明授权
    • Method to form liquid crystal displays using a triple damascene technique
    • 使用三重镶嵌技术形成液晶显示器的方法
    • US6159759A
    • 2000-12-12
    • US443423
    • 1999-11-19
    • Kai ShaoCerdin LeeYi XuShao-Fu Sanford Chu
    • Kai ShaoCerdin LeeYi XuShao-Fu Sanford Chu
    • G02F1/1335G02F1/1362H01L21/00
    • G02F1/133553G02F1/136277
    • A new method of forming liquid crystal displays has been achieved. Metal conductors are provided in an insulating layer overlying a semiconductor substrate. A first isolation layer is deposited. A first silicon nitride layer is deposited. The first silicon nitride layer is patterned to form openings for planned vias overlying the metal conductors. A second isolation layer is deposited. A second silicon nitride layer is deposited. The second silicon nitride layer is patterned to form masks overlying where dummy supports for the metal pixels are planned and to form openings to extend the planned vias. A third isolation layer is deposited. The third isolation layer is patterned to form openings for the planned metal pixels. The second isolation layer and the first isolation layer are etched through to complete the vias and the dummy supports. A metal layer is deposited filling the openings for the metal pixels, the dummy support, and the vias. The metal layer is polished down to the top surface of the third isolation layer to complete the metal pixels. A thin film passivation is deposited. A liquid crystal layer is deposited. A transparent image point electrode is formed to complete the liquid crystal display.
    • 已经实现了一种形成液晶显示器的新方法。 金属导体设置在覆盖半​​导体衬底的绝缘层中。 沉积第一隔离层。 沉积第一氮化硅层。 图案化第一氮化硅层以形成覆盖金属导体的计划通孔的开口。 沉积第二隔离层。 沉积第二氮化硅层。 图案化第二氮化硅层以形成掩模,覆盖着金属像素的虚拟支撑被设计并形成扩展计划的通孔的开口。 沉积第三个隔离层。 图案化第三隔离层以形成用于计划的金属像素的开口。 蚀刻第二隔离层和第一隔离层以完成通孔和虚拟支撑。 沉积金属层,填充用于金属像素,虚拟支撑件和通孔的开口。 金属层被抛光到第三隔离层的顶表面以完成金属像素。 沉积薄膜钝化。 沉积液晶层。 形成透明图像点电极以完成液晶显示器。
    • 60. 发明申请
    • Prokaryotic collage-like proteins and uses thereof
    • 原核拼贴样蛋白及其用途
    • US20100184085A1
    • 2010-07-22
    • US12660596
    • 2010-03-02
    • Magnus HöökSlawomir LukomskiYi Xu
    • Magnus HöökSlawomir LukomskiYi Xu
    • G01N33/53C07K16/00C12N15/63C12N1/21C12P21/06
    • C07K14/78
    • The present invention provides recombinant triple helical proteins or collagen-like proteins comprising a prokaryotic protein or one or more domains of a prokaryotic protein comprising a collagen-like peptide sequence of repeated Gly-Xaa-Yaa triplets and, optionally, one or more domains from a mammalian collagen. Also provided are expression vectors and host cells containing the expression vectors to produce these recombinant proteins and methods of producing the same. Additionally, antibodies are provided that are directed against a recombinant collagen-like protein that, preferably, binds an integrin. Furthermore, a method of screening for potential therapeutic compounds that inhibit the integrin-binding or integrin-interacting activities of recombinant collagen-like proteins.
    • 本发明提供重组三螺旋蛋白或胶原样蛋白,其包含原核蛋白或原核蛋白的一个或多个结构域,其包含重复Gly-Xaa-Yaa三联体的胶原样肽序列和任选的一个或多个结构域 哺乳动物胶原蛋白。 还提供了含有表达载体以产生这些重组蛋白的表达载体和宿主细胞及其生产方法。 此外,提供针对重组胶原样蛋白的抗体,其优选结合整联蛋白。 此外,筛选抑制重组胶原样蛋白的整联蛋白结合或整联蛋白相互作用活性的潜在治疗化合物的方法。