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51. 发明授权

US06185173B2 Sampled amplitude read channel employing a trellis sequence detector matched to a channel code constraint and a post processor for correcting errors in the detected binary sequence using the signal samples and an error syndrome 失效
标题翻译：使用与信道码约束匹配的网格序列检测器的采样幅度读取信道和用于使用信号样本校正检测到的二进制序列中的错误的后处理器和误差综合征
公开(公告)号：US06185173B2
公开(公告)日：2001-02-06
申请号：US09127101
申请日：1998-07-31
申请人： Jay N. Livingston , William G. Bliss
发明人： Jay N. Livingston , William G. Bliss
IPC分类号： G11B700
CPC分类号： G11B20/10055 , G11B20/10037 , G11B20/1426 , H03M13/00
摘要： A sampled amplitude read channel is disclosed for disk storage systems comprising a encoder/decoder for implementing a high rate channel code that codes out specific minimum distance error events of a trellis sequence detector by enforcing a particular code constraint. The trellis sequence detector comprises a state machine matched to the code constraint which effectively removes the corresponding minimum distance errors from the detected output sequence. Additionally, the channel code encodes redundancy bits into the write data for implementing an error detection code. The redundancy bits are processed during a read operation to generate an error syndrome used to detect and correct other dominant error events, such as the NRZ (+) and (+−+) error events. In this manner, the most likely error events of the trellis sequence detector are either coded out by the channel code constraint, or detected and corrected using the error syndrome. As a result, the present invention provides a significant distance enhancing performance gain over the prior art without decreasing the system's code rate, thereby providing a substantial increase in linear bit density and overall storage capacity.
摘要翻译：公开了一种用于磁盘存储系统的采样幅度读取通道，其包括用于实现高速率信道码的编码器/解码器，该高速率信道码通过执行特定的码约束来编码网格序列检测器的特定最小距离误差事件。网格序列检测器包括与代码约束匹配的状态机，其有效地从检测到的输出序列中去除对应的最小距离误差。另外，通道代码将冗余位编码到写入数据中，以实现错误检测码。在读取操作期间处理冗余位以产生用于检测和校正其他主要错误事件（例如NRZ（+）和（+ - +））错误事件的错误校正。以这种方式，网格序列检测器的最可能的错误事件或者通过信道码约束进行编码，或使用误差综合征检测和校正。结果，本发明提供了超过现有技术的显着的距离增强性能增益，而不降低系统的码率，从而提供线性位密度和总体存储容量的显着增加。

52. 发明授权

US6157604A Sampled amplitude read channel employing a baud rate estimator for digital timing recovery in an optical disk storage device 失效
标题翻译：采用波特率估计器的采样幅度读取通道用于光盘存储设备中的数字定时恢复
公开(公告)号：US6157604A
公开(公告)日：2000-12-05
申请号：US80559
申请日：1998-05-18
申请人： German S. Feyh , Jim Graba , William G. Bliss
发明人： German S. Feyh , Jim Graba , William G. Bliss
IPC分类号： G11B20/14 , G11B27/30 , H03L7/091 , H03M13/41 , H04N5/85 , H04N5/76
CPC分类号： G11B20/10037 , G11B20/10055 , G11B20/10296 , G11B20/1403 , G11B27/3027 , H03L7/091 , H03M13/41 , H03M13/6331 , H03M13/6505 , H03M13/6563 , H03M13/6569 , H04N5/85 , G11B2020/10916 , G11B2220/2545 , G11B2220/2562
摘要： A sampled amplitude read channel for optical disk storage systems is disclosed comprising an all digital timing recovery circuit. The RF read signal from the read head is sampled asynchronous to the baud rate and the asynchronous sample values are interpolated to generate sample values that are substantially synchronous to the baud rate. A data detector, such as a Viterbi sequence detector, processes the synchronous sample values to generate an estimated binary sequence representing the recorded binary sequence. The timing recovery circuit comprises a baud rate estimator for estimating the baud rate relative to the sampling rate, wherein the estimated baud rate is used to initialize a timing recovery loop filter at the end of seek operations. The all digital timing recovery circuit and baud rate estimator enable the storage device to begin reading the user data immediately after a seek operation, rather than wait for the CLV servo loop to acquire the target spindle speed.
摘要翻译：公开了一种用于光盘存储系统的采样幅度读取通道，其包括全数字定时恢复电路。来自读取头的RF读取信号与波特率异步采样，并且内插异步采样值以产生与波特率基本同步的采样值。诸如维特比序列检测器的数据检测器处理同步采样值以产生表示记录的二进制序列的估计二进制序列。定时恢复电路包括用于估计相对于采样率的波特率的波特率估计器，其中所估计的波特率用于在搜索操作结束时初始化定时恢复环路滤波器。全数字定时恢复电路和波特率估计器使存储设备能够在搜索操作之后立即开始读取用户数据，而不是等待CLV伺服循环获取目标主轴转速。

53. 发明授权

US6009549A Disk storage system employing error detection and correction of channel coded data, interpolated timing recovery, and retroactive/split-segment symbol synchronization 失效
标题翻译：磁盘存储系统采用通道编码数据的错误检测和校正，内插定时恢复和追溯/分段符号同步
公开(公告)号：US6009549A
公开(公告)日：1999-12-28
申请号：US856885
申请日：1997-05-15
申请人： William G. Bliss , Christopher P. Zook , Richard T. Behrens
发明人： William G. Bliss , Christopher P. Zook , Richard T. Behrens
IPC分类号： G11B5/012 , G11B20/10 , G11B20/14 , G11B20/18 , G11B27/30 , C11C29/00 , G11B5/09
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1426 , G11B20/1833 , G11B27/3027 , G11B2020/1476 , G11B5/012
摘要： A disk storage system is disclosed wherein user data received from a host system is first encoded according to a first channel code having a high code rate, and then encoded according to an ECC code, such as a Reed-Solomon code, wherein the ECC redundancy symbols are encoded according to a second channel code having low error propagation. In the preferred embodiment, the first channel code is a RLL (d,k) code having a long k constraint which allows for longer block lengths (and higher code rates). During read back, a synchronous read channel samples the analog read signal a synchronously and interpolates the asynchronous sample values to generate sample values substantially synchronized to the baud rate. In contrast to conventional synchronous-sampling timing recovery, interpolated timing recovery can tolerate a longer RLL k constraint because it is less sensitive to noise in the read signal and not affected by process variations in fabrication. Additionally, a trellis sequence detector detects an estimated binary sequence from the synchronous sample values, wherein a state transition diagram of the trellis detector is configured according to the code constraints of the first and second channel codes. The estimated binary sequence output by the sequence detector is buffered in a data buffer to facilitate the error detection and correction process, and to allow for retroactive and split-segment symbol synchronization using multiple sync marks.
摘要翻译：公开了一种磁盘存储系统，其中根据具有高码率的第一信道码首先对从主机系统接收的用户数据进行编码，然后根据诸如Reed-Solomon码的ECC码进行编码，其中ECC冗余符号根据具有低误差传播的第二信道码进行编码。在优选实施例中，第一信道码是具有长k约束的RLL（d，k）码，其允许更长的码块长度（和较高码率）。在读回期间，同步读通道同步地对模拟读取信号进行采样，并内插异步采样值，以生成基本上与波特率同步的采样值。与传统的同步采样定时恢复相比，内插定时恢复可以容忍较长的RLL k约束，因为它对读取信号中的噪声不太敏感，并且不受制造过程变化的影响。另外，网格序列检测器根据同步采样值检测估计的二进制序列，其中根据第一和第二信道码的编码约束配置网格检测器的状态转移图。由序列检测器输出的估计的二进制序列被缓冲在数据缓冲器中，以便于错误检测和校正过程，并允许使用多个同步标记进行追溯和分段符号同步。

54. 发明授权

US5987634A Channel quality circuit in a sampled amplitude read channel 失效
标题翻译：通道质量电路采样振幅读通道
公开(公告)号：US5987634A
公开(公告)日：1999-11-16
申请号：US897339
申请日：1997-07-21
申请人： Richard T. Behrens , William G. Bliss , William R. Foland, Jr.
发明人： Richard T. Behrens , William G. Bliss , William R. Foland, Jr.
IPC分类号： G11B20/10 , G11C29/00
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037
摘要： A channel quality circuit, incorporated within a sampled amplitude read channel utilized in a magnetic storage system, for processing and accumulating performance data from the individual read channel components, wherein the performance data is used to calibrate the read channel to operate in a particular environment, to estimate the bit error rate of the storage system, and to detect defects in the magnetic medium. The channel quality circuit generates a test pattern of digital data which is written to the storage system. Then, as the test pattern is read from the storage system, the channel quality circuit accumulates performance data from the read channel components. The test pattern is used to generate expected samples and expected sample errors relative to the samples read by the read channel. Gating logic is programmed to accumulate only the particular performance data of interest. The channel quality circuit computes auto and cross-correlations, squared errors, and threshold comparisons. A defect detection filter detects particular defects in the media. In order to predict the bit error rate of the storage system, the channel quality circuit accumulates noise auto-correlation data, confidence metrics from a sequence detector, and cross-correlation of expected sample errors with actual sample errors.
摘要翻译：一种信道质量电路，其被并入在磁存储系统中使用的采样幅度读取信道中，用于处理和累积来自各个读取信道分量的性能数据，其中，所述性能数据用于校准所述读取信道以在特定环境中操作，估计存储系统的误码率，并检测磁介质中的缺陷。信道质量电路产生写入存储系统的数字数据的测试模式。然后，当从存储系统读取测试图案时，信道质量电路从读取的信道分量累积性能数据。测试模式用于产生相对于读通道读取的样本的预期样本和预期样本误差。门控逻辑被编程为仅累积感兴趣的特定性能数据。信道质量电路计算自动和互相关，平方误差和阈值比较。缺陷检测滤波器检测介质中的特定缺陷。为了预测存储系统的误码率，信道质量电路将噪声自相关数据，序列检测器的置信度量度以及预期样本误差与实际样本误差的互相关累积。

55. 发明授权

US5966258A Asynchronous/synchronous digital gain control loop in a sampled amplitude read channel 失效
标题翻译：采样幅度读通道中的异步/同步数字增益控制环路
公开(公告)号：US5966258A
公开(公告)日：1999-10-12
申请号：US859980
申请日：1997-05-21
申请人： William G. Bliss
发明人： William G. Bliss
IPC分类号： G11B5/012 , G11B5/09 , G11B5/55 , G11B5/58 , G11B5/596 , G11B19/28 , G11B20/10 , G11B20/12 , G11B20/14
CPC分类号： G11B20/10055 , G11B19/28 , G11B20/10009 , G11B20/10037 , G11B20/1403 , G11B5/012 , G11B5/09 , G11B5/5526 , G11B5/553 , G11B5/5547 , G11B5/58 , G11B5/59605 , G11B5/59622 , G11B5/59633 , G11B5/59688 , G11B20/1258 , G11B5/5534 , G11B5/5965
摘要： A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete-time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a variable gain amplifier for adjusting the magnitude of the analog read signal before sampling, and a discrete-time gain control loop for generating a gain control signal applied to the VGA in response to the discrete-time sample values. The discrete-time sample values may, or may not be, synchronized to a baud rate of the recorded data. For example, when reading the user data the discrete-time sample values are synchronous, and when reading a servo address mark (SAM) the sample values are asynchronous. As such, the discrete-time gain control loop of the present invention is programmable to operate in a synchronous or asynchronous mode. In asynchronous mode, the gain error is computed in a manner that is less sensitive to amplitude fluctuations over long blocks of data. This is accomplished by computing the gain error as the difference between a predetermined set point and the maximum absolute sample value over a programmable block length.
摘要翻译：公开了一种采样幅度读取通道，用于通过从位于盘存储介质上的读取头的模拟读取信号中的采样脉冲的一系列离散时间采样值中检测估计的二进制序列来读取记录在盘存储介质上的数据。读通道包括用于调整采样之前的模拟读取信号的幅度的可变增益放大器和用于响应于离散时间采样值产生施加到VGA的增益控制信号的离散时间增益控制环路。离散时间采样值可以或可以不与记录数据的波特率同步。例如，当读取用户数据时，离散时间采样值是同步的，并且当读取伺服地址标记（SAM）时，采样值是异步的。因此，本发明的离散时间增益控制环路可编程为以同步或异步模式操作。在异步模式下，增益误差的计算方式对长数据块的幅度波动较不敏感。这是通过将增益误差计算为在可编程块长度上的预定设定点和最大绝对样本值之间的差来实现的。

56. 发明授权

US5961658A PR4 equalization and an EPR4 remod/demod sequence detector in a sampled amplitude read channel 失效
标题翻译： PR4均衡和EPR4重调/解调序列检测器
公开(公告)号：US5961658A
公开(公告)日：1999-10-05
申请号：US862492
申请日：1997-05-23
申请人： David E. Reed , William G. Bliss , Lisa C. Sundell
发明人： David E. Reed , William G. Bliss , Lisa C. Sundell
IPC分类号： G11B20/18 , H03M13/00 , H03M13/12
CPC分类号： H03M13/6343 , G11B20/10277 , H03M13/098 , H03M13/3776 , H03M13/41 , H03M5/145 , G11B20/10064 , G11B20/10074 , G11B20/10175 , G11B2020/1446 , G11B2220/2516
摘要： A sampled amplitude read channel is disclosed for disk storage systems that employs an EPR4 remod/demod sequence detector. To reduce the complexity of timing recovery, gain control and adaptive equalization, the channel samples are initially equalized into a PR4 partial response so that a simple slicer circuit can generate estimated sample values. The PR4 equalized channel samples are then passed through a 1+D filter to generate EPR4 equalized channel samples which are processed by an EPR4 Viterbi sequence detector to generate a preliminary binary sequence. The preliminary binary sequence is remodulated into an estimated or ideal PR4 sample sequence which is subtracted from the PR4 equalized channel samples to generate an error sample sequence. An error pattern detector processes the error sample sequence to detect the dominant error events associated with the EPR4 Viterbi sequence detector.
摘要翻译：公开了采用EPR4重构/解调序列检测器的磁盘存储系统的采样幅度读取通道。为了降低定时恢复的复杂度，增益控制和自适应均衡，信道样本最初被均衡为PR4部分响应，使得简单的限幅电路可以产生估计的采样值。然后将PR4均衡信道样本通过1 + D滤波器以产生由EPR4维特比序列检测器处理以产生初步二进制序列的EPR4均衡信道样本。将初步二进制序列重新调制成从PR4均衡信道样本中减去的估计或理想PR4采样序列，以生成误差采样序列。误差模式检测器处理误差采样序列以检测与EPR4维特比序列检测器相关的主要误差事件。

57. 发明授权

US5926490A Sampled amplitude read channel employing a remod/demod sequence detector guided by an error syndrome 失效
标题翻译：采用由误差综合征引导的重构/解调序列检测器的采样幅度读取通道
公开(公告)号：US5926490A
公开(公告)日：1999-07-20
申请号：US862493
申请日：1997-05-23
申请人： David E. Reed , William G. Bliss , Lisa C. Sundell
发明人： David E. Reed , William G. Bliss , Lisa C. Sundell
IPC分类号： G11B20/10 , G06F11/00
CPC分类号： G11B20/1403 , G11B20/10009 , G11B20/10037 , G11B20/10055
摘要： A sampled amplitude read channel is disclosed for disk storage systems that employs a remod/demod sequence detector guided by an error syndrome of an error detection code (EDC). The remod/demod sequence detector comprises: a conventional trellis type maximum likelihood sequence detector, such as a Viterbi detector, for detecting a preliminary binary sequence from the channel sample values; a syndrome generator for generating an error syndrome in response to the preliminary binary sequence; a remodulator for remodulating the detected binary sequence into a sequence of estimated ideal sample values; a sample error generator for subtracting the channel samples from the estimated samples to generate a sample error sequence; an error pattern detector for detecting potential error events in the sample error sequence; and an error corrector for correcting the preliminary binary sequence when the error syndrome indicates that an error occurred. In the embodiment disclosed herein, the error syndrome is generated as the parity over a predetermined number of bits. When a parity error occurs, a correction is made corresponding to the most likely error event detected. Guiding the remod/demod sequence detector with an error syndrome avoids miscorrections that may otherwise occur in conventional remod/demod sequence detectors.
摘要翻译：公开了采用由错误检测码（EDC）的误差综合征引导的重构/解调序列检测器的磁盘存储系统的采样幅度读取通道。重构/解调序列检测器包括：常规网格型最大似然序列检测器，例如维特比检测器，用于从信道样本值检测初步二进制序列; 一种用于响应于初步二进制序列产生误差综合征的综合征发生器; 用于将所检测的二进制序列重新调制成估计的理想样本值的序列的再调制器; 用于从估计样本中减去信道样本以产生样本误差序列的采样误差发生器; 用于检测样本误差序列中的潜在误差事件的误差模式检测器; 以及错误校正器，用于当错误校正器指示发生错误时校正初步二进制序列。在本文公开的实施例中，错误校正器被生成为超过预定位数的奇偶校验。当发生奇偶校验错误时，对应于检测到的最可能的错误事件进行校正。引导具有错误综合征的重构/解调序列检测器避免了传统的重构/解调序列检测器可能发生的误差。

58. 发明授权

US5903857A Method and apparatus for calibrating an analog filter in a sampled amplitude read channel 失效
标题翻译：用于校准采样振幅读通道中的模拟滤波器的方法和装置
公开(公告)号：US5903857A
公开(公告)日：1999-05-11
申请号：US751832
申请日：1996-11-18
申请人： Richard T. Behrens , Tyson Tuttle , Kent D. Anderson , Trent O. Dudley , William G. Bliss
发明人： Richard T. Behrens , Tyson Tuttle , Kent D. Anderson , Trent O. Dudley , William G. Bliss
IPC分类号： G11B20/10 , G06F17/10 , G11B5/035
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/10481
摘要： A method and apparatus for calibrating an analog equalizer in a sampled amplitude read channel is disclosed wherein the filter's frequency response is measured and calibrated directly. This is accomplished by injecting a known periodic signal into the analog filter and measuring a spectrum value at a predetermined frequency. The filter parameters are adjusted accordingly until the spectrum reaches a predetermined target value. In the preferred embodiment, the analog filter comprises at least one second order low pass filter (referred to as a biquad filter), and the filter's spectrum is adjusted relative to the well known parameters f.sub.o and Q. Specifically, the parameters f.sub.o and Q are optimized relative to a power measurement at predetermined harmonics of the input signal. In this manner, the present invention enables auto-calibration of the analog equalizer without reading any data from the disc. Furthermore, the calibration process can be executed during the storage system's normal operation without significantly degrading its overall performance.
摘要翻译：公开了一种用于校准采样振幅读通道中的模拟均衡器的方法和装置，其中滤波器的频率响应被直接测量和校准。这是通过将已知的周期信号注入模拟滤波器并以预定频率测量频谱值来实现的。相应地调整滤波器参数，直到频谱达到预定的目标值。在优选实施例中，模拟滤波器包括至少一个二阶低通滤波器（称为双二阶滤波器），并且相对于众所周知的参数fo和Q调节滤波器的频谱。具体地，参数fo和Q是相对于输入信号的预定谐波处的功率测量而优化。以这种方式，本发明能够在不从盘读取任何数据的情况下自动校准模拟均衡器。此外，可以在存储系统的正常操作期间执行校准过程，而不会显着降低其整体性能。

59. 发明授权

US5854714A Digital servo demodulation for sampled amplitude magnetic recording 失效
标题翻译：数字伺服解调采样振幅磁记录
公开(公告)号：US5854714A
公开(公告)日：1998-12-29
申请号：US741156
申请日：1996-10-29
申请人： David E. Reed , William G. Bliss
发明人： David E. Reed , William G. Bliss
IPC分类号： G11B5/596 , G11B21/08 , G11B21/10 , G11B5/09
CPC分类号： G11B21/083 , G11B21/085 , G11B21/106 , G11B5/59655 , G11B5/59688 , G11B20/10037 , G11B20/10055
摘要： A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts. A plurality of registers store the amplitude measurement of corresponding servo bursts such as the four servo bursts in a quadrature system. The sample values are interpolated, squared, and the sampling frequency dithered in order to decrease the sensitivity of the burst amplitude measurement to variations in the sampling phase and to increase the effective resolution of the read channel ADC for servo demodulation. Control signals are generated in response to the detected servo data which are transferred to a servo controller over a fully digital interface, thus obviating the analog-to-digital converter found in conventional servo controllers.
摘要翻译：一种并入采样振幅读通道内的离散时间伺服解调技术，用于解调存储在磁介质上的嵌入式伺服场信息。伺服字段信息由读取头转换为模拟信号，并转换为读通道中的一系列采样值。解调技术响应于采样值，并且包括用于检测伺服数据的离散时间峰值检测器和用于测量伺服脉冲串幅度的离散时间伺服脉冲串幅度检测器。通过从样本值序列感测斜率的变化，在模拟读取信号中检测峰。峰由极性限定，只有当峰的极性与前一峰的符号相反时才检测到峰。通过内插，整流和累加对应于伺服脉冲串的采样值序列来测量伺服脉冲串幅度。多个寄存器将相应伺服脉冲串的振幅测量值存储在正交系统中，例如四个伺服脉冲串。样本值被内插，平方，并且采样频率抖动，以便将脉冲串幅度测量的灵敏度降低到采样相位的变化并且增加用于伺服解调的读通道ADC的有效分辨率。响应于通过全数字接口传送到伺服控制器的检测到的伺服数据产生控制信号，从而避免了在常规伺服控制器中发现的模拟 - 数字转换器。

60. 发明授权

US5802118A Sub-sampled discrete time read channel for computer storage systems 失效
标题翻译：用于计算机存储系统的子采样离散时间读通道
公开(公告)号：US5802118A
公开(公告)日：1998-09-01
申请号：US681578
申请日：1996-07-29
申请人： William G. Bliss , David E. Reed , Richard T. Behrens
发明人： William G. Bliss , David E. Reed , Richard T. Behrens
IPC分类号： G11B20/10 , G11B20/14 , H04B1/10
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/10037 , G11B20/1426
摘要： A sampled amplitude read channel is disclosed for reading binary data from a computer disk storage system, wherein the read channel sub-samples an analog read signal at a rate lower than the baud rate and detects the binary data from the sub-sampled values using a sequence detector. In one embodiment, the sub-sampled values are interpolated to generate synchronous sample values which are processed by a conventional sequence detector. In another embodiment, the sequence detector is modified to detect the binary data directly from the sub-sampled values. In yet another embodiment, the sequence detector comprises a remodulator and an error pattern detector for detecting and correcting bit errors in the detected binary data. In addition, for the various embodiments a channel code increases the distance property of the sequence detector in order to compensate for the degradation in performance caused by sub-sampling.
摘要翻译：公开了一种用于从计算机磁盘存储系统读取二进制数据的采样幅度读取通道，其中读取通道以低于波特率的速率对模拟读取信号进行子采样，并使用以下方式从子采样值检测二进制数据：序列检测器。在一个实施例中，子采样值被内插以产生由常规序列检测器处理的同步采样值。在另一个实施例中，修改序列检测器以直接从子采样值检测二进制数据。在另一个实施例中，序列检测器包括重调制器和用于检测和校正检测到的二进制数据中的比特错误的错误模式检测器。此外，对于各种实施例，信道码增加了序列检测器的距离特性，以便补偿由次采样引起的性能下降。

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