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51. 发明授权

US06979898B1 Semiconductor component and a method of fabricating the semiconductor component 失效
标题翻译：半导体元件及其制造方法
公开(公告)号：US06979898B1
公开(公告)日：2005-12-27
申请号：US09420086
申请日：1999-10-18
申请人： Warren M. Farnworth , Alan G. Wood
发明人： Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L21/48 , H05K3/02 , H01L23/04 , H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/3128 , G01R1/0483 , G01R3/00 , G01R31/2867 , H01L21/4846 , H01L23/32 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/49 , H01L24/72 , H01L2224/05554 , H01L2224/05599 , H01L2224/48227 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/10161 , H01L2924/12042 , H01L2924/3011 , H01L2924/30111 , H05K1/0218 , H05K1/113 , H05K3/027 , H05K2201/09363 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A semiconductor component and a method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The semiconductor component includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.
摘要翻译：提供了一种半导体元件和用于制造诸如印刷电路板，多芯片模块，芯片级封装和测试载体之类的半导体元件的方法。半导体部件包括提供其上具有覆盖层的导电层的衬底。使用激光加工工艺，在导电层中形成凹槽以限定衬底上的导体图案。导体可以形成为期望的尺寸和间隔，并且可以包括诸如接合焊盘，导电通孔和外部球接触的特征。此外，所选择的导体可以配置为共面接地或电压迹线，用于调整配置为信号迹线的其他导体中的阻抗值。

52. 发明授权

US06974725B2 Interconnections for a semiconductor device 失效
标题翻译：半导体器件的互连
公开(公告)号：US06974725B2
公开(公告)日：2005-12-13
申请号：US10808713
申请日：2004-03-23
申请人： Walter L. Moden , Larry D. Kinsman , Warren M. Farnworth
发明人： Walter L. Moden , Larry D. Kinsman , Warren M. Farnworth
IPC分类号： H01L23/31 , H01L23/485 , H01L21/44
CPC分类号： H01L24/10 , H01L23/3107 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/05568 , H01L2224/05573 , H01L2224/05599 , H01L2224/13 , H01L2224/13099 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/85399 , H01L2224/8592 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01027 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/00014 , H01L2924/00 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/00013 , H01L2924/013
摘要： A method for forming an electrical contact for a semiconductor device comprises the steps of providing a semiconductor wafer section having a major surface with a plurality of conductive pads thereon and electrically coupling each pad with an elongated electrical interconnect. Next, each electrical interconnect is encased in a dielectric and the dielectric is sectioned to expose a portion of each interconnect. An inventive structure which can be formed by the inventive method is also described.
摘要翻译：一种用于形成用于半导体器件的电接触的方法包括以下步骤：提供具有主表面的半导体晶片部分，其上具有多个导电焊盘，并使每个焊盘与细长的电互连电连接。接下来，每个电互连被封装在电介质中，并且电介质被分段以暴露每个互连的一部分。还描述了可以通过本发明方法形成的本发明的结构。

53. 发明授权

US06896837B2 Layer thickness control for stereolithography utilizing variable liquid elevation and laser focal length 失效
公开(公告)号：US06896837B2
公开(公告)日：2005-05-24
申请号：US10225945
申请日：2002-08-22
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： B29C35/08 , B29C67/00 , B29C41/02 , B29C70/72
CPC分类号： B29C64/135 , B29C2035/0838 , B29C2037/903 , B29K2995/0073 , B33Y10/00 , B33Y30/00 , B33Y40/00
摘要： An apparatus and method for controlling the surface level of a liquid residing within a relatively vertically stationary workpiece support platform disposed within a reservoir for use in stereolithographic processes wherein a layered object or structure is formed by selectively curing portions of the liquid to at least a semisolid state in multiple, at least partially superimposed layers. Providing precise control of liquid depth over the vertically stationary platform as well as focusing of a laser beam for curing the liquid at the varying surface levels thereof relative to the vertically stationary platform is effected using a laser range finder system controlled by a computer used to control the stereolithographic process in a closed loop fashion.

54. 发明授权

US06890844B2 Methods and apparatus for forming solder balls 有权
标题翻译：用于形成焊球的方法和装置
公开(公告)号：US06890844B2
公开(公告)日：2005-05-10
申请号：US10630051
申请日：2003-07-30
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： B22F9/08 , B23K35/02 , B23K35/14 , H05K3/12 , H05K3/34 , H01L21/44 , B02K35/14
CPC分类号： H05K3/3484 , B22F9/08 , B22F2009/0808 , B23K35/0244 , H05K3/1216 , H05K3/3478 , H05K2201/09745 , H05K2201/2081 , H05K2203/0338 , H05K2203/043 , H05K2203/0557
摘要： Methods and apparatus for forming a plurality of uniformly sized solder balls utilize a stencil having a plurality of holes of uniform volume disposed on a substrate. Solder is disposed in the holes of the stencil on the substrate. Typically, the solder is in the form of solder paste which is distributed into the holes using a squeegee. While within the holes of the stencil on the substrate, the solder is melted to form solder balls. The stencil may then be removed to leave the solder balls on the substrate, or the solder balls may be removed while the stencil remains on the substrate.
摘要翻译：用于形成多个均匀尺寸的焊球的方法和设备利用具有设置在基板上的具有均匀体积的多个孔的模版。焊料设置在基板上的模板的孔中。通常，焊料是焊膏的形式，其使用刮刀分配到孔中。在衬底上的模板的孔内，焊料熔化形成焊球。然后可以去除模板以将焊球留在衬底上，或者当模板保留在衬底上时可以去除焊球。

55. 发明授权

US06858891B2 Nanotube semiconductor devices and methods for making the same 失效
标题翻译：纳米管半导体器件及其制造方法
公开(公告)号：US06858891B2
公开(公告)日：2005-02-22
申请号：US10315511
申请日：2002-12-09
申请人： Warren M. Farnworth , Kevin G. Duesman
发明人： Warren M. Farnworth , Kevin G. Duesman
IPC分类号： G11C13/02 , H01L21/8234 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L27/28 , H01L29/76 , H01L51/05 , H01L51/30 , H01L29/94
CPC分类号： G11C13/025 , B82Y10/00 , G11C13/0033 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/28 , H01L51/0048 , H01L51/0508 , H01L51/057 , Y10S977/734 , Y10S977/742 , Y10S977/773 , Y10S977/813 , Y10S977/842 , Y10S977/843 , Y10S977/89 , Y10S977/935 , Y10S977/943
摘要： Provided herein are vertical nanotube semiconductor devices and methods for making the same. An embodiment of the semiconductor devices comprises a vertical transistor/capacitor cell including a nanotube. The device includes a vertical transistor and a capacitor cell both using a single nanotube to form the individual devices.
摘要翻译：本文提供了垂直纳米管半导体器件及其制造方法。半导体器件的实施例包括具有纳米管的垂直晶体管/电容器单元。该器件包括垂直晶体管和电容器单元，两者都使用单个纳米管来形成各个器件。

56. 发明授权

US06841796B2 Substrate mapping 有权
标题翻译：基板映射
公开(公告)号：US06841796B2
公开(公告)日：2005-01-11
申请号：US10280200
申请日：2002-10-25
申请人： Warren M. Farnworth , Derek J. Gochnour
发明人： Warren M. Farnworth , Derek J. Gochnour
IPC分类号： H01L23/544 , H01L23/55
CPC分类号： H01L23/544 , H01L24/83 , H01L2223/54413 , H01L2223/5442 , H01L2223/54473 , H01L2223/54486 , H01L2224/83192 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , Y10T29/49004 , Y10T29/49146 , Y10T29/53043 , Y10T29/53178 , Y10T29/53187 , H01L2924/00
摘要： A method and apparatus relating to fabricating semiconductor die packages including a mounting substrate and dice attached thereto. The mounting substrate includes multiple die attach sites and a designator having substrate identification information. The die attach sites are evaluated and categorized as either good or defective die attach sites, wherein the evaluated information is saved in an electronic file as mapped information. A die attach apparatus attaches dice to the die attach sites in accord with the mapped information, wherein known good dice are attached to the good die attach sites and known defective dice are attached to the defective die attach sites. The assembly is then encapsulated in a transfer molding operation.
摘要翻译：涉及制造半导体管芯封装的方法和装置，包括安装衬底和附着于其上的裸片。安装基板包括多个管芯附接位置和具有衬底识别信息的指示符。芯片附着位点被评估并分类为良好或有缺陷的裸片附着位点，其中所评估的信息作为映射信息保存在电子文件中。芯片连接装置根据映射信息将裸片附着到裸片附着位置，其中已知的良好裸片附着到裸片附着位置，并且已知的有缺陷的裸片附着到有缺陷的裸片附着位置上。然后将组件封装在传递模制操作中。

57. 发明授权

US06841423B2 Methods for formation of recessed encapsulated microelectronic devices 失效
标题翻译：凹陷封装微电子器件的形成方法
公开(公告)号：US06841423B2
公开(公告)日：2005-01-11
申请号：US10320892
申请日：2002-12-16
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： H01L21/56 , H01L21/68 , H01L23/31 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/85001 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method for manufacturing microelectronic device packages. In one embodiment, the device package can include a support member having a first surface, a second surface facing opposite the first surface and a cavity extending through the support member from the first surface to the second surface. A microelectronic device is disposed in the cavity and is supported in the cavity with a removable retention member. The microelectronic device is electrically coupled to the support member and is partially surrounded with an encapsulating material. The removable retention member is then removed to expose a surface of the microelectronic device. Accordingly, the package can have a low profile because the encapsulating material does not surround one of the microelectronic device surfaces. In one embodiment, a heat conductive material can be engaged with the exposed surface of the microelectronic device to increase the rate at which heat is transferred away from the microelectronic device.
摘要翻译：微电子器件封装的制造方法。在一个实施例中，装置包装可以包括具有第一表面，与第一表面相对的第二表面的支撑构件和从第一表面延伸穿过支撑构件到第二表面的空腔。微电子器件设置在空腔中并且用可移除的保持构件支撑在空腔中。微电子器件电耦合到支撑构件并且被封装材料部分地包围。然后去除可移除的保持构件以暴露微电子器件的表面。因此，由于封装材料不包围微电子器件表面之一，所以封装可以具有低的外形。在一个实施例中，导热材料可以与微电子器件的暴露表面接合以增加热量从微电子器件转移的速率。

58. 发明授权

US06825547B2 Semiconductor device including edge bond pads 失效
标题翻译：半导体器件包括边缘焊盘
公开(公告)号：US06825547B2
公开(公告)日：2004-11-30
申请号：US10137766
申请日：2002-05-02
申请人： Warren M. Farnworth , Larry D. Kinsman , Walter L. Moden
发明人： Warren M. Farnworth , Larry D. Kinsman , Walter L. Moden
IPC分类号： H01L2348
CPC分类号： H01L24/11 , H01L23/485 , H01L24/02 , H01L24/45 , H01L2224/02371 , H01L2224/0401 , H01L2224/13099 , H01L2224/45144 , H01L2224/45147 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15787 , H01L2924/3011 , H01L2224/48 , H01L2924/00
摘要： A vertically mountable semiconductor device including at least one bond pad disposed on an edge thereof. The bond pad includes a conductive bump disposed thereon. The semiconductor device may also include a protective overcoat layer. The present invention also includes a method of fabricating the semiconductor device, including forming disconnected notches in a semiconductor wafer, redirecting circuit traces into each of the notches, and singulating the semiconductor wafer along the notches to form bond pads on the edges of the resultant semiconductor devices. A method of attaching the semiconductor device to a carrier substrate includes orienting the semiconductor device such that the bond pad is aligned with a corresponding terminal of the carrier substrate and establishing an electrical connection between the bond pad and the terminal. Preferably, an electrically conductive material is disposed between the bond pad and the terminal to establish an electrically conductive bond between the semiconductor device and the carrier substrate.
摘要翻译：一种垂直安装的半导体器件，包括设置在其边缘上的至少一个接合焊盘。接合焊盘包括设置在其上的导电凸块。半导体器件还可以包括保护外涂层。本发明还包括一种制造半导体器件的方法，包括在半导体晶片中形成断开的切口，将电路迹线重定向到每个凹口中，以及沿着凹口划分半导体晶片，以在所得半导体的边缘上形成接合焊盘设备。将半导体器件附接到载体衬底的方法包括使半导体器件定向，使得接合焊盘与载体衬底的相应端子对准并且在接合焊盘和端子之间建立电连接。优选地，导电材料设置在接合焊盘和端子之间，以在半导体器件和载体衬底之间建立导电接合。

59. 发明授权

US06819003B2 Recessed encapsulated microelectronic devices and methods for formation 有权
标题翻译：嵌入式微电子器件和形成方法
公开(公告)号：US06819003B2
公开(公告)日：2004-11-16
申请号：US10320882
申请日：2002-12-16
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： H01L2328
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/85001 , H01L2224/85399 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic device package and method for manufacture. In one embodiment, the device package can include a support member having a first surface, a second surface facing opposite the first surface and a cavity extending through the support member from the first surface to the second surface. A microelectronic device is disposed in the cavity and is supported in the cavity with a removable retention member. The microelectronic device is electrically coupled to the support member and is partially surrounded with an encapsulating material. The removable retention member is then removed to expose a surface of the microelectronic device. Accordingly, the package can have a low profile because the encapsulating material does not surround one of the microelectronic device surfaces. In one embodiment, a heat conductive material can be engaged with the exposed surface of the microelectronic device to increase the rate at which heat is transferred away from the microelectronic device.
摘要翻译：一种微电子器件封装及其制造方法。在一个实施例中，装置包装可以包括具有第一表面，与第一表面相对的第二表面的支撑构件和从第一表面延伸穿过支撑构件到第二表面的空腔。微电子器件设置在空腔中并且用可移除的保持构件支撑在空腔中。微电子器件电耦合到支撑构件并且被封装材料部分地包围。然后去除可移除的保持构件以暴露微电子器件的表面。因此，由于封装材料不包围微电子器件表面之一，所以封装可以具有低的外形。在一个实施例中，导热材料可以与微电子器件的暴露表面接合以增加热量从微电子器件转移的速率。

60. 发明授权

US06814778B1 Method for continuous mode solder jet apparatus 失效
标题翻译：连续式焊料喷射装置的方法
公开(公告)号：US06814778B1
公开(公告)日：2004-11-09
申请号：US09435455
申请日：1999-11-05
申请人： Warren M. Farnworth
发明人： Warren M. Farnworth
IPC分类号： B05D106
CPC分类号： H01L21/6715 , B23K3/0623 , B41J2/09 , H01L21/67144 , H05K3/3457 , H05K2203/105 , H05K2203/163
摘要： A solder jet apparatus is disclosed The solder jet apparatus is a continuous mode solder jet that includes a blanking system and raster scan system. The use of the raster scan and blanking systems allows for a continuous stream of solder to be placed anywhere on the surface in any desired X-Y plane. This allows for greater accuracy as well as greater product throughput. Additionally, with the raster scan system, repairs to existing soldered surfaces can be quickly and easily performed using a map of the defects for directing the solder to the defects.
摘要翻译：公开了一种焊料喷射装置。焊料喷射装置是包括消隐系统和光栅扫描系统的连续模式焊料喷射。光栅扫描和消隐系统的使用允许将连续的焊料流放置在任何所需的X-Y平面上的任何地方。这允许更高的精度以及更大的产品吞吐量。另外，使用光栅扫描系统，可以使用用于将焊料引导到缺陷的缺陷图快速轻松地进行现有焊接表面的修复。

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