专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

51. 发明授权

US06606273B1 Methods and systems for flash memory tunnel oxide reliability testing 失效
标题翻译：闪存隧道氧化物可靠性测试方法与系统
公开(公告)号：US06606273B1
公开(公告)日：2003-08-12
申请号：US10121140
申请日：2002-04-11
申请人： Xin Guo , Nian Yang , Zhigang Wang
发明人： Xin Guo , Nian Yang , Zhigang Wang
IPC分类号： G11C700
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/006 , G11C29/50
摘要： Methods are disclosed for determining tunnel oxide reliability of flash memory devices in a wafer prior to sorting and packaging without damaging or stressing the devices. The methods comprise measuring an initial threshold voltage of a test cell having the same tunnel oxide as other flash cells on the wafer, applying an erase stress to the test cell for a first time period and a program stress to the test cell for a second time period, and measuring the final threshold voltage of the test cell. The difference between the initial and final threshold voltages is then used to determine or estimate the tunnel oxide reliability of the flash memory cells on the wafer.
摘要翻译：公开了用于在分选和包装之前确定晶片中闪存器件的隧道氧化物可靠性的方法，而不会损坏或强调器件。该方法包括测量具有与晶片上的其它闪存单元相同的隧道氧化物的测试单元的初始阈值电压，将第一时间段的擦除应力施加到测试单元上，并且向测试单元施加程序应力第二次周期，并测量测试单元的最终阈值电压。然后使用初始阈值电压和最终阈值电压之间的差异来确定或估计晶片上闪存单元的隧道氧化物可靠性。

52. 发明授权

US07724075B2 Method to provide a higher reference voltage at a lower power supply in flash memory devices 有权
标题翻译：在闪存器件中的较低电源处提供较高参考电压的方法
公开(公告)号：US07724075B2
公开(公告)日：2010-05-25
申请号：US11634776
申请日：2006-12-06
申请人： Tien-Chun Yang , Yonggang Wu , Nian Yang
发明人： Tien-Chun Yang , Yonggang Wu , Nian Yang
IPC分类号： G05F1/575
CPC分类号： G11C5/147 , G05F3/08 , G11C16/30
摘要： A fast reference circuit having active feedback includes a bias supply circuit and a variable divider circuit connected by an active feedback path to the bias supply circuit, and a comparator circuit connected to the variable divider circuit, the bias supply circuit, and a reference node of the variable divider circuit. In one embodiment, a start-up circuit initially discharges a potential at the bias supply and comparator circuits, then initializes a reference voltage at the reference node at about zero volts to improve repeatability. In one embodiment, the variable voltage divider comprises an impendence that is trimmed based on a sheet resistance of a process used to fabricate the fast reference circuit, and further comprises a variable reference current circuit coupled to the impedance and configured to generate a current having a value based on a desired reference voltage and to conduct the current through the impedance, thereby generating the reference voltage associated therewith. The comparator circuit is configured to compare the bias supply voltage to the reference voltage, and drive the bias supply and the variable divider circuit in response to the comparison, thereby quickly stabilizing the reference voltage.
摘要翻译：具有有源反馈的快速参考电路包括偏置电源电路和通过有源反馈路径连接到偏置电源电路的可变分频器电路，以及连接到可变分频器电路，偏置电源电路和参考节点的参考节点可变分频电路。在一个实施例中，启动电路首先在偏置电源和比较器电路处放电，然后在约零伏特的参考节点初始化参考电压，以提高可重复性。在一个实施例中，可变分压器包括基于用于制造快速参考电路的工艺的薄层电阻而修整的阻抗，并且还包括耦合到阻抗的可变参考电流电路，并且被配置为产生具有基于所需参考电压的值，并且将电流传导通过阻抗，由此产生与其相关联的参考电压。比较器电路被配置为将偏置电源电压与参考电压进行比较，并且响应于比较来驱动偏置电源和可变分频器电路，由此快速稳定参考电压。

53. 发明申请

US20090147587A1 CIRCUIT PRE-CHARGE TO SENSE A MEMORY LINE 有权
标题翻译：电路预先感知记忆线
公开(公告)号：US20090147587A1
公开(公告)日：2009-06-11
申请号：US11951262
申请日：2007-12-05
申请人： Tien-Chun Yang , Yonggang Wu , Nian Yang
发明人： Tien-Chun Yang , Yonggang Wu , Nian Yang
IPC分类号： G11C16/00
CPC分类号： G11C16/30 , G11C7/12 , G11C16/24
摘要： Commonly, read times of a memory line are slowed due to voltage overshoot and/or voltage undershoot. To eliminate these problems, a control component can manage voltage while a leakage component manages timing of voltage. This allows for a line pre-charge that produces increase read times. The control component can implement as a variable resistor that modifies value to compensate for temperature. The leakage component can include a capacitor configuration that allows voltage to pass.
摘要翻译：通常，存储线的读取时间由于电压过冲和/或电压下冲而变慢。为了消除这些问题，控制部件可以管理电压，同时泄漏部件管理电压的时序。这允许产生增加读取时间的线路预充电。控制组件可以实现一个可变电阻器来修改值来补偿温度。泄漏部件可以包括允许电压通过的电容器配置。

54. 发明授权

US07460415B2 Drain voltage regulator 有权
标题翻译：漏电压调节器
公开(公告)号：US07460415B2
公开(公告)日：2008-12-02
申请号：US11639936
申请日：2006-12-15
申请人： Yonggang Wu , Nian Yang , Tien-Chun Yang
发明人： Yonggang Wu , Nian Yang , Tien-Chun Yang
IPC分类号： G11C5/14
CPC分类号： G11C7/16 , G11C5/147 , G11C7/12
摘要： A voltage regulator comprises resistor elements that mitigate variations in a program voltage (VPROG). In particular, the resistors allow copies of the voltage regulator to be fabricated more consistently across a semiconductor substrate. As such, variations in respective program voltages applied to different bitlines of a memory arrangement are mitigated. This mitigates yield loss as more devices perform as desired, thus necessitating fewer discards.
摘要翻译：电压调节器包括减轻编程电压（VPROG）变化的电阻元件。特别地，电阻允许电压调节器的副本在半导体衬底上更一致地制造。因此，减轻了施加到存储器装置的不同位线的各个编程电压的变化。随着越来越多的设备按需要执行，这减轻了产量损失，因此需要更少的丢弃物。

55. 发明授权

US06898124B1 Efficient and accurate sensing circuit and technique for low voltage flash memory devices 有权
标题翻译：高效，准确的低压闪存器件感测电路和技术
公开(公告)号：US06898124B1
公开(公告)日：2005-05-24
申请号：US10678446
申请日：2003-10-03
申请人： Zhigang Wang , Nian Yang , Yue-Song He
发明人： Zhigang Wang , Nian Yang , Yue-Song He
IPC分类号： G11C11/56 , G11C16/06 , G11C16/26
CPC分类号： G11C16/26 , G11C11/5642
摘要： An exemplary sensing circuit comprises a first transistor connected to a first node, where a target memory cell has a drain capable of being connected to the first node through a selection circuit during a read operation involving the target memory cell. The sensing circuit further comprises a decouple circuit which is connected to the first transistor. The decouple circuit includes a second transistor having a gate coupled to a gate of the first transistor. The decouple circuit further has a decouple coefficient (N) greater than 1. The drain of the second transistor is connected at a second node to a reference voltage through a bias resistor. With the arrangement, the drain of the second transistor generates a sense amp input voltage at the second node such that the sense amp input voltage is decoupled from the first node.
摘要翻译：示例性感测电路包括连接到第一节点的第一晶体管，其中目标存储器单元具有能够在涉及目标存储器单元的读取操作期间通过选择电路连接到第一节点的漏极。感测电路还包括连接到第一晶体管的去耦电路。解耦电路包括具有耦合到第一晶体管的栅极的栅极的第二晶体管。去耦电路还具有大于1的去耦系数（N）。第二晶体管的漏极通过偏置电阻器在第二节点连接到参考电压。利用该布置，第二晶体管的漏极在第二节点处产生感测放大器输入电压，使得感测放大器输入电压与第一节点分离。

56. 发明授权

US06884638B1 METHOD OF FABRICATING A FLASH MEMORY SEMICONDUCTOR DEVICE BY DETERMINING THE ACTIVE REGION WIDTH BETWEEN SHALLOW TRENCH ISOLATION STRUCTURES USING AN OVERDRIVE CURRENT MEASUREMENT TECHNIQUE AND A DEVICE THEREBY FABRICATED 有权
标题翻译：通过使用超导电流测量技术和具有制造能力的器件确定微透镜分离结构之间的活性区域宽度来制造闪速存储器半导体器件的方法
公开(公告)号：US06884638B1
公开(公告)日：2005-04-26
申请号：US10225052
申请日：2002-08-20
申请人： Tien-Chun Yang , Nian Yang , Zhigang Wang
发明人： Tien-Chun Yang , Nian Yang , Zhigang Wang
IPC分类号： H01L21/336 , H01L23/544 , H01L21/66
CPC分类号： H01L29/66825 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a flash memory device by determining the active region width (10) of a semiconductor device (27) using a measuring technique for the source drain overdrive current elements (31, 32, 33) having different active region widths and using that difference to establish the difference between the active region width of the devices (31, 32, 33) and the drawn width and using the difference to establish the actual width (10) from drawn width in future devices, and a device thereby fabricated.
摘要翻译：一种用于通过使用具有不同有源区宽度的源极漏极过驱动电流元件（31,32,33）的测量技术来确定半导体器件（27）的有源区宽度（10）来制造闪速存储器件的方法，并且使用该方法以确定器件（31,32,33）的有效区域宽度与绘制宽度之间的差异，并且使用差值来确定未来器件中的绘制宽度的实际宽度（10），以及由此制造的器件。

57. 发明授权

US06828623B1 Floating gate memory device with homogeneous oxynitride tunneling dielectric 有权
标题翻译：具有均匀氧氮化物隧道电介质的浮栅存储器件
公开(公告)号：US06828623B1
公开(公告)日：2004-12-07
申请号：US10232487
申请日：2002-08-30
申请人： Xin Guo , Nian Yang , Zhigang Wang
发明人： Xin Guo , Nian Yang , Zhigang Wang
IPC分类号： H01L29788
CPC分类号： H01L29/518 , H01L21/28273 , H01L29/7885
摘要： A memory device with homogeneous oxynitride tunneling dielectric. Specifically, the present invention describes a flash memory cell that includes a tunnel oxide dielectric layer including homogeneous oxynitride. The tunnel oxide dielectric layer separates a floating gate from a channel region that is formed between a source region and a drain region in a substrate. The flash memory cell further includes a dielectric layer that separates a control gate from the floating gate. In one case, the homogenous oxynitride is a defect free silicon nitride. The homogeneity of the oxynitride is due to the uniform distribution of nitride within the tunnel oxide dielectric layer. Further, the use of the homogeneous oxynitride can increase the dielectric constant and lower the barrier height of the tunnel oxide dielectric layer for increased performance. Also, the homogenous oxynitride supports source-side channel hot hole erasing in the flash memory cell.
摘要翻译：具有均匀氧氮化物隧道电介质的存储器件。具体地，本发明描述了一种闪存单元，其包括包括均匀氮氧化物的隧道氧化物介电层。隧道氧化物电介质层将浮置栅极与形成在衬底中的源极区域和漏极区域之间的沟道区域分离。闪存单元还包括将控制栅极与浮动栅极分离的介质层。在一种情况下，均匀的氮氧化合物是无缺陷的氮化硅。氧氮化物的均匀性是由于氮化物在隧道氧化物介电层内的均匀分布。此外，为了提高性能，使用均匀的氮氧化物可以增加介电常数并降低隧道氧化物介电层的势垒高度。此外，均匀的氮氧化物支持闪存单元中的源极侧通道热孔擦除。

58. 发明授权

US06822259B1 Method of detecting and distinguishing stack gate edge defects at the source or drain junction 有权
标题翻译：在源极或漏极结处检测和区分堆叠栅极边缘缺陷的方法
公开(公告)号：US06822259B1
公开(公告)日：2004-11-23
申请号：US10126193
申请日：2002-04-19
申请人： Zhigang Wang , Nian Yang , Xin Guo
发明人： Zhigang Wang , Nian Yang , Xin Guo
IPC分类号： H01L2358
CPC分类号： H01L21/28273 , G11C16/04 , G11C29/006 , G11C2029/0403 , G11C2029/5002
摘要： A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed (710). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions (720). Subsequent to the stressing, a drain current versus gate voltage relationship is measured (730). The sequence of programming, stressing and measuring may be repeated (740) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified (750) as associated with a source edge or a drain edge. In this novel manner, stack gate edge defects may be identified and localized via non-destructive means, and corrective actions to the semiconductor manufacturing process and/or the partially manufactured wafer may be taken.
摘要翻译：一种用于测试包括堆叠浮栅结构的半导体的方法和装置。浮动门被编程（710）。电应力或干扰电压在特定条件（720）中用源极和漏极施加到控制栅极。在应力之后，测量漏极电流与栅极电压的关系（730）。编程，应力和测量的顺序可以重复（740），具有不同的源和漏源条件。更具体地，在将源极保持在地面的同时将漏极保持在接地处时，将正和负偏压施加到源极，并且在将源保持在地面的同时将类似的偏压施加到漏极。通过检查在该应力应用序列之后采取的测量信息，可以将源极边缘或漏极边缘的叠栅极边缘缺陷识别（750）。以这种新颖的方式，可以通过非破坏性手段识别和定位堆叠栅极边缘缺陷，并且可以采取对半导体制造工艺和/或部分制造的晶片的校正动作。

59. 发明授权

US06797650B1 Flash memory devices with oxynitride dielectric as the charge storage media 有权
标题翻译：具有氧氮化物介质的闪存器件作为电荷存储介质
公开(公告)号：US06797650B1
公开(公告)日：2004-09-28
申请号：US10342032
申请日：2003-01-14
申请人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
发明人： Zhigang Wang , Nian Yang , John Jianshi Wang , Jiang Li
IPC分类号： H01L2131
CPC分类号： H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L21/3144 , H01L21/3145 , H01L29/513 , H01L29/518
摘要： One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si3N4)x(SiO2)(1-x), where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.
摘要翻译：本发明的一个方面涉及将电荷存储在基本上化学计量的氮氧化硅电介质中的闪存器件。化学计量的氮氧化硅电介质可由式（Si 3 N 4）x（SiO 2）（1-x）表示，其中x为0-1。基本上化学计量的氮氧化硅电介质具有不符合上述公式的相对较少的原子。本发明的闪速存储器件具有比可比较的SONOS型闪存器件更少的缺陷和更低的泄漏。本发明的另一方面涉及通过FTIR，折射率测量或两者的组合来评估化学计量。

60. 发明授权

US06734080B1 Semiconductor isolation material deposition system and method 失效
标题翻译：半导体隔离材料沉积系统及方法
公开(公告)号：US06734080B1
公开(公告)日：2004-05-11
申请号：US10159078
申请日：2002-05-31
申请人： Nian Yang , John Jianshi Wang , Tien-Chun Yang
发明人： Nian Yang , John Jianshi Wang , Tien-Chun Yang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： A semiconductor isolation material deposition system and method that facilitates convenient and efficient integrated multi-step deposition of isolation regions is presented. In one embodiment of the present invention, an integrated circuit includes densely configured component areas and sparsely configured component areas. An active area in a wafer is created and a shallow trench space is formed. A thin layer of TEOS isolation material layer is deposited on top of the active area and the shallow trench. For example, the layer of thin layer of TEOS isolation material is in a range of 4000 to 5000 angstroms thick over the top of underlying active areas. A reverse mask and pre-planarization etch is performed on the thin layer of TEOS isolation material. The remaining TEOS edge spikes between the densely configured component area and the sparsely configured component area are minimal (e.g., about 500 angstroms. The remaining excess oxidant and silicon nitride are removed utilizing chemical mechanical polishing processes. In one exemplary implementation, the present invention facilitates an integrated approach to STI fabrication processes that achieve successful high yielding results by considering the impacts of one process step on another.
摘要翻译：介绍了半导体隔离材料沉积系统及其方法，便于实现隔离区域的多步沉积。在本发明的一个实施例中，集成电路包括密集配置的组件区域和稀疏配置的组件区域。产生晶片中的有效区域并形成浅沟槽空间。 TEOS隔离材料层的薄层沉积在有源区域和浅沟槽的顶部。例如，薄层的TEOS隔离材料层的厚度在下面有效区域顶部的4000至5000埃的范围内。在TEOS隔离材料的薄层上进行反掩模和预平面化蚀刻。在密集配置的部件区域和稀疏构造的部件区域之间的剩余的TEOS边缘尖峰是最小的（例如，约500埃），使用化学机械抛光工艺去除剩余的多余的氧化剂和氮化硅。在一个示例性实施方式中，通过考虑一个工艺步骤对另一个工艺步骤的影响，可以获得成功的高产量结果的STI制造工艺的综合方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式