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51. 发明授权

US06436771B1 Method of forming a semiconductor device with multiple thickness gate dielectric layers 有权
标题翻译：形成具有多个厚度栅极电介质层的半导体器件的方法
公开(公告)号：US06436771B1
公开(公告)日：2002-08-20
申请号：US09902895
申请日：2001-07-12
申请人： Syun-Ming Jang , Chen-Hua Yu , Mong-Song Liang
发明人： Syun-Ming Jang , Chen-Hua Yu , Mong-Song Liang
IPC分类号： H01L218234
CPC分类号： H01L21/823462 , Y10S438/981
摘要： Process sequences used to simultaneously form a first dielectric gate layer for a first group of MOSFET elements, and a second dielectric gate layer for a second group of MOSFET elements, with the thickness of the first dielectric gate layer different than the thickness of the second gate dielectric layer, has been developed. A first iteration of this invention entails a remote plasma nitridization procedure used to form a thin silicon nitride layer on a bare, first portion of a semiconductor substrate, while simultaneously forming a thin silicon oxynitride layer on the surface of a first silicon dioxide layer, located on second portion of the semiconductor substrate. A thermal oxidation procedure than results in the formation of a thin second silicon dioxide layer, on the first portion of the semiconductor substrate, underlying the thin silicon nitride layer, while the first silicon dioxide layer, underlying the silicon oxynitride component of the composite dielectric layer, only increases slightly in thickness. A second iteration of this invention features the formation of a silicon nitride—first silicon dioxide, composite gate layer, on a first portion of a semiconductor substrate, with the composite gate layer used to retard oxidation during a thermal oxidation procedure used growth to form a second silicon dioxide layer, on a second portion of the semiconductor substrate.
摘要翻译：用于同时形成用于第一组MOSFET元件的第一电介质栅极层和用于第二组MOSFET元件的第二电介质栅极层的工艺序列，其中第一电介质栅极层的厚度不同于第二栅极的厚度电介质层，已经开发。本发明的第一次迭代需要用于在半导体衬底的裸露的第一部分上形成薄氮化硅层的远程等离子体氮化过程，同时在第一二氧化硅层的表面上形成薄的氮氧化硅层，所述第一二氧化硅层位于在半导体衬底的第二部分上。一种热氧化方法，其结果是在半导体衬底的第一部分上形成薄的第二二氧化硅层，位于薄氮化硅层下面，同时第一二氧化硅层位于复合介电层的氮氧化硅组分下面，厚度仅略有增加。本发明的第二次迭代的特征在于在半导体衬底的第一部分上形成氮化硅 - 第一二氧化硅复合栅极层，其中用于在热氧化过程中延迟氧化的复合栅极层用于生长以形成第二二氧化硅层，在半导体衬底的第二部分上。

52. 发明授权

US06423625B1 Method of improving the bondability between Au wires and Cu bonding pads 有权
标题翻译：提高Au线和Cu焊盘之间的粘接性的方法
公开(公告)号：US06423625B1
公开(公告)日：2002-07-23
申请号：US09385754
申请日：1999-08-30
申请人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
发明人： Syun-Ming Jang , Mong-Song Liang , Chen-Hua Yu , Chung-Shi Liu , Jane-Bai Lai
IPC分类号： H01L2160
CPC分类号： H01L24/05 , H01L23/53238 , H01L24/03 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/0401 , H01L2224/04042 , H01L2224/05001 , H01L2224/05006 , H01L2224/05083 , H01L2224/05147 , H01L2224/05624 , H01L2224/05647 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/48624 , H01L2224/48647 , H01L2224/48699 , H01L2224/48724 , H01L2224/48747 , H01L2924/01007 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： Cu, for its rather loe resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.
摘要翻译：铜，因其相当的电阻率，将广泛应用于二分之一微米级ULSI器件。然而，众所周知，Cu在空气中容易被腐蚀。在芯片的封装中，由此制成Cu的焊盘将氧化。此外，Au球和Cu垫之间的反应非常差。另一方面，厚度约3-4nm的天然AlOx层将在Al中暴露于空气中形成; 形成的层是惰性的并且能够保护Al免于腐蚀。此外，Au球和Al之间的反应非常好。因此，利用本发明的方法，在用于成功的Au布线的Cu焊盘上实施作为胶水和保护层的Al或AlCu。

53. 发明授权

US06372664B1 Crack resistant multi-layer dielectric layer and method for formation thereof 有权
标题翻译：耐裂纹多层电介质层及其形成方法
公开(公告)号：US06372664B1
公开(公告)日：2002-04-16
申请号：US09419104
申请日：1999-10-15
申请人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Yu
发明人： Syun-Ming Jang , Chu-Yun Fu , Chen-Hua Yu
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/76801
摘要： A method for forming upon a substrate employed within a microelectronics fabrication a dieletric layer with improved physical properties. There is first provided a substrate. There is then formed over the substrate a series of lines which constitute a patterned microelectronics layer. There is then formed over the patterned microelectronics layer and substrate a conformal dielectric layer. There is then formed over the substrate a second dielectric layer. There is then formed over the substrate a third dielectric layer formed of silicon oxide dielectric material employing high density plasma chemical vapor deposition (HDP-CVD) to complete a composite inter-level metal dielectric (IMD) layer. A fourth dielectric layer formed employing silicon containing dielectric material may be formed over the substrate and third dielectric layer to complete an inter-level metal dielectric (IMD) layer. The fourth dielectric layer is inhibited from cracking by the presence of the third silicon oxide dielectric layer formed by HDP-CVD method.
摘要翻译：一种用于在微电子制造中使用的衬底上形成具有改进的物理性质的抗蚀层的方法。首先提供基板。然后在衬底上形成构成图案化微电子层的一系列线。然后在图案化的微电子层和衬底上形成共形介电层。然后在衬底上形成第二介电层。然后在衬底上形成由使用高密度等离子体化学气相沉积（HDP-CVD）的氧化硅介电材料形成的第三介电层，以完成复合层间金属电介质（IMD）层。可以在衬底和第三电介质层上形成使用含硅电介质材料形成的第四电介质层，以完成层间金属电介质（IMD）层。通过存在由HDP-CVD法形成的第三氧化硅电介质层，可以抑制第四绝缘层的破裂。

54. 发明授权

US06329717B1 Integrated circuit having selectivity deposited silicon oxide spacer layer formed therein 失效
标题翻译：在其中形成有选择性淀积的氧化硅间隔层的集成电路
公开(公告)号：US06329717B1
公开(公告)日：2001-12-11
申请号：US08616140
申请日：1996-03-14
申请人： Syun-Ming Jang , Chen-Hua Yu , Lung Chen , Lin-June Wu
发明人： Syun-Ming Jang , Chen-Hua Yu , Lung Chen , Lin-June Wu
IPC分类号： H01L2348
CPC分类号： H01L21/76801
摘要： A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is formed through an ozone assisted Chemical Vapor Deposition (CVD) process employing Tetra Ethyl Ortho Silicate as the silicon source material. The silicon oxide insulator spacer layer is formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.
摘要翻译：一种用于在集成电路内的多层图案化金属堆叠之间选择性地沉积氧化硅绝缘体间隔层的方法。形成在半导体衬底上的是通过等离子体增强化学气相沉积（PECVD）工艺形成的氧化硅绝缘体衬底层。在氧化硅绝缘体衬底层形成多层图案化的金属叠层时。多层图案化的金属堆叠具有由氮化钛形成的顶部阻挡金属层和由含铝合金形成的下部导体金属层。在通过多层图案化的金属堆叠暴露的氧化硅绝缘体基底层的部分上并且通过多层图案化的金属堆叠暴露的含铝合金的边缘上选择性地形成氧化硅绝缘体间隔层。氧化硅绝缘体间隔层通过使用四乙基正硅酸盐作为硅源材料的臭氧辅助化学气相沉积（CVD）工艺形成。形成氧化硅绝缘体间隔层，用于在由氮化钛形成的顶部阻挡金属层上形成氧化硅绝缘体间隔层的沉积时间不超过孵育时间。

55. 发明授权

US06228760B1 Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE-OXIDE进行接触或通过照相和氧化物和W化学机械抛光的缺陷还原
公开(公告)号：US06228760B1
公开(公告)日：2001-05-08
申请号：US09263563
申请日：1999-03-08
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介电层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在二电层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

56. 发明授权

US06197669B1 Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process 有权
标题翻译：通过低温，高压LPCVD工艺生长的非晶硅上减少表面缺陷
公开(公告)号：US06197669B1
公开(公告)日：2001-03-06
申请号：US09292361
申请日：1999-04-15
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L213205
CPC分类号： C23C16/24 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262
摘要： A method is provided for depositing an amorphous silicon thin film on a substrate. The method is carried out in a reactor chamber and can be a LPCVD, PECVD or RTCVD process. The method comprises introducing a gas species into the reactor chamber for a time sufficient to dehydrate the substrate and to form a thin layer of silicon on the substrate. Following formation of the thin layer of silicon, a dopant gas is introduced into the reactor chamber to form the doped silicon thin film. The temperature and pressure within the chamber is set to minimize formation of surface irregularities or pits within the thin amorphous silicon layer.
摘要翻译：提供了一种在衬底上沉积非晶硅薄膜的方法。该方法在反应器室中进行，并且可以是LPCVD，PECVD或RTCVD工艺。该方法包括将气体物质引入反应器室中足以使基底脱水并在基底上形成薄的硅层的时间。在形成薄层的硅之后，将掺杂剂气体引入反应器室以形成掺杂的硅薄膜。室内的温度和压力被设定为使薄的非晶硅层内的表面凹凸或凹坑的形成最小化。

57. 发明授权

US6143673A Method for forming gap filling silicon oxide intermetal dielectric (IMD) layer formed employing ozone-tEOS 有权
标题翻译：用臭氧tEOS形成间隙填充氧化硅金属间电介质（IMD）层的方法
公开(公告)号：US6143673A
公开(公告)日：2000-11-07
申请号：US409888
申请日：1999-10-01
申请人： Syun-Ming Jang , Ying-Ho Chen , Shwangming Jeng , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Shwangming Jeng , Chen-Hua Yu
IPC分类号： H01L21/311 , H01L21/316 , H01L21/31
CPC分类号： H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/02315 , H01L21/31116 , H01L21/31612
摘要： A method for forming within a microelectronics fabrication a dielectric layer formed over, around and between patterned conductor layers. There is first provided a substrate employed within a microelectronics fabrication upon which is formed a patterned conductor layers. There is then formed over the patterned conductor layer a silicon oxide dielectric layer. There is then treated the silicon oxide dielectric layer to an anisotropic sputter etching process to remove silicon oxide dielectric material without re-deposition from the bottom of the gap between lines of the patterned conductor layer and to reform the silicon oxide dielectric layers on the sidewalls of the patterned lines to form spacer layers thereon. Both the silicon oxide dielectric layer deposition process and the sputter etching process may be repeated as desired to form the desired depth of trench and shape of spacer layer. There is then exposed the substrate to a nitrogen plasma. There is then formed over the substrate a gap filling silicon oxide dielectric layer to complete the formation of the inter-level dielectric layer with minimal void content in gaps between patterned lines.
摘要翻译：在微电子制造中形成在图案化导体层之上，周围和之间形成介电层的方法。首先提供在微电子制造中使用的衬底，其上形成图案化的导体层。然后在图案化的导体层上形成氧化硅介电层。然后将氧化硅介电层处理成各向异性溅射蚀刻工艺以去除氧化硅介电材料，而不从图案化导体层的线之间的间隙的底部重新沉积，并且重新形成在图案化导体层的侧壁上的氧化硅介电层图案化线以在其上形成间隔层。可以根据需要重复氧化硅介电层沉积工艺和溅射蚀刻工艺，以形成期望的沟槽深度和间隔层的形状。然后将基板暴露于氮等离子体。然后在衬底上形成填充氧化硅介电层的间隙，以在图案化线之间的间隙中以最小的空隙含量完成层间电介质层的形成。

58. 发明授权

US6121111A Method of removing tungsten near the wafer edge after CMP 有权
标题翻译：在CMP之后去除晶片边缘附近的钨的方法
公开(公告)号：US6121111A
公开(公告)日：2000-09-19
申请号：US234093
申请日：1999-01-19
申请人： Syun-Ming Jang , Chen-Hua Yu , Shwangming Jeng
发明人： Syun-Ming Jang , Chen-Hua Yu , Shwangming Jeng
IPC分类号： H01L21/321 , H01L21/3213 , H01L21/76 , G03C5/00 , H01L21/301 , H01L21/44 , H01L23/544
CPC分类号： H01L21/3212 , H01L21/32136 , H01L2223/54493
摘要： A method is described for removing residual metal, such as tungsten, from the edge region of a wafer. After tungsten is deposited on a wafer to fill via holes in a dielectric the wafer is planarized using Chemical Mechanical Polishing, CMP. The CMP does not remove the tungsten from the edge of the wafer. After conductor metals for a layer of conducting electrodes has been deposited a layer of photoresist is formed on the wafer and patterned to clear the metals from over the alignment marks. This photoresist is then removed from the edge region of the wafer. The residual metals are then etched away from the edge region of the wafer using the remaining photoresist as a mask during the same etching step used to remove metals from the alignment marks or during a separate etching step. In one embodiment the alignment marks and laser marks are relocated to the edge region of the wafer and the residual metals are etched away from the edge region of the wafer during the same etching step used to remove metals from the alignment marks and laser marks.
摘要翻译：描述了从晶片的边缘区域去除诸如钨的残留金属的方法。在钨沉积在晶片上以填充电介质中的孔之后，使用化学机械抛光CMP将晶片平坦化。 CMP不会从晶片的边缘去除钨。在已经沉积了导电电极层的导体金属之后，在晶片上形成了一层光致抗蚀剂并被图案化以从对准标记上方清除金属。然后将该光致抗蚀剂从晶片的边缘区域移除。然后，在用于从对准标记中移除金属或在单独的蚀刻步骤期间的相同蚀刻步骤期间，使用剩余的光致抗蚀剂作为掩模，将残余金属从晶片的边缘区域蚀刻掉。在一个实施例中，将对准标记和激光标记重新定位到晶片的边缘区域，并且在用于从对准标记和激光标记去除金属的相同蚀刻步骤期间，残留的金属被从晶片的边缘区域蚀刻掉。

59. 发明授权

US06049137A Readable alignment mark structure formed using enhanced chemical mechanical polishing 失效
标题翻译：使用增强的化学机械抛光形成可读取的对准标记结构
公开(公告)号：US06049137A
公开(公告)日：2000-04-11
申请号：US106331
申请日：1998-06-29
申请人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chung-Long Chang , Chen-Hua Yu
IPC分类号： H01L23/544 , H01L21/302 , H01L21/461
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48. Etches are used to remove the residual insulating layer 46A, silicon nitride layer 44, and pad oxide layer 42 in the alignment mark area 30 thereby exposing the alignment marks 48 and making the alignment marks readable.
摘要翻译：可读取的对准标记的结构和在半导体衬底上的对准标记区域中制造可读取的对准标记的方法。提供了包括产品区域12和对准标记区域30的半导体衬底10。对准标记区域30具有外部区域40和内部区域50.外部区域40围绕内部区域50.多个对准标记沟槽24形成在内部区域50内的衬底10中。衬垫氧化物层20 并且在至少对准标记区域12中顺序地形成氮化硅层44.隔离沟槽43至少在外部区域40中形成在基板10中。绝缘层46至少形成在对准标记区域30的上方绝缘层46进行化学机械抛光，从而从内部对准标记区域50除去绝缘层的第一厚度，并且在对准标记沟槽48中留下残留绝缘层46A。使用蚀刻来去除残留绝缘层46A ，氮化硅层44和衬垫氧化物层42，从而露出对准标记48并使对准标记可读。

60. 发明授权

US6043136A Trench filling method employing oxygen densified gap filling CVD silicon oxide layer 失效
标题翻译：使用氧致密化间隙填充的沟槽填充方法形成具有低臭氧浓度的CVD氧化硅层
公开(公告)号：US6043136A
公开(公告)日：2000-03-28
申请号：US121710
申请日：1998-07-24
申请人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Chen-Hua Yu
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： A method for forming a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a silicon oxide layer, where the silicon oxide layer is formed through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material at an ozone:TEOS volume ratio of from about 10:1 to about 14:1. Finally, there is then annealed thermally the substrate within an oxygen containing atmosphere at a temperature of greater than about 1100 degrees centigrade to form from the silicon oxide layer a densified silicon oxide layer. The densified silicon oxide layer formed employing the method is formed with an unexpectedly low shrinkage.
摘要翻译：一种形成氧化硅层的方法。首先提供基板。然后在衬底上形成氧化硅层，其中通过使用臭氧氧化剂和四乙基原硅酸盐（TEOS）的臭氧辅助亚大气压力热化学气相沉积（SACVD）方法形成氧化硅层）硅源材料：TEOS体积比为约10:1至约14:1。最后，在含氧气氛中，在大于约1100摄氏度的温度下将衬底热处理，从氧化硅层形成致密氧化硅层。使用该方法形成的致密氧化硅层形成意想不到的低收缩率。

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