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51. 发明授权

US07504689B2 Semiconductor device and manufacturing method of semiconductor device 失效
标题翻译：半导体器件及半导体器件的制造方法
公开(公告)号：US07504689B2
公开(公告)日：2009-03-17
申请号：US11182013
申请日：2005-07-15
申请人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
发明人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , G11C16/0433 , H01L21/2815 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.
摘要翻译：提供了一种具有分割栅极结构的非易失性半导体存储器件，其中存储栅极形成在凸形基板上，并且其侧表面用作沟道。根据本发明的非易失性半导体存储器件即使存储单元按比例缩小，读取电流驱动功率也优异。

52. 发明申请

US20070207581A1 Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same 有权
公开(公告)号：US20070207581A1
公开(公告)日：2007-09-06
申请号：US11797839
申请日：2007-05-08
申请人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/4232 , H01L29/792
摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.

53. 发明授权

US07259422B1 Nonvolatile semiconductor memory device and its fabrication method 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07259422B1
公开(公告)日：2007-08-21
申请号：US11653832
申请日：2007-01-17
申请人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Daisuke Okada
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： A memory cell includes a selective gate and a memory gate arranged on one side surface of the selective gate. The memory gate includes one part formed on one side surface of the selective gate and the other part electrically isolated from the selective gate and a p-well through an ONO layer formed below the memory gate. A sidewall-shaped silicon oxide is formed on side surfaces of the selective gate, and a sidewall-shaped silicon dioxide layer and a silicon dioxide layer are formed on side surfaces of the memory gate. The ONO layer formed below the memory gate is terminated below the silicon oxide, and prevents generation of a low breakdown voltage region in the silicon oxide near an end of the memory gate during deposition of the silicon dioxide layer.
摘要翻译：存储单元包括布置在选择栅极的一个侧表面上的选择栅极和存储栅极。存储器栅极包括形成在选择栅极的一个侧表面上的一个部分和与选择栅极电隔离的另一部分，以及通过形成在存储栅极下方的ONO层的p阱。在选择栅极的侧面上形成侧壁状的氧化硅，在存储栅的侧面形成侧壁状的二氧化硅层和二氧化硅层。形成在存储器栅下方的ONO层终止在氧化硅的下方，并且防止在沉积二氧化硅层期间在存储栅的端部附近的硅氧化物中产生低的击穿电压区域。

54. 发明授权

US07247890B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07247890B2
公开(公告)日：2007-07-24
申请号：US10931119
申请日：2004-09-01
申请人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
发明人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
IPC分类号： H01L31/0328 , H01L29/80
CPC分类号： H01L29/66659 , H01L27/10855 , H01L27/10873 , H01L27/10894 , H01L29/1079 , H01L29/6656 , H01L29/7835
摘要： Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.
摘要翻译：这里公开了具有在存储单元中具有MISFET阈值电压的较小散射并具有良好的电容保持性的DRAM的半导体器件，以及半导体器件的制造方法。在光氧化之前，在栅电极的侧壁上形成抗氧化膜，从而抑制栅电极的侧壁的氧化，并且在不对称扩散区域结构中减少形成在侧壁上的膜的厚度的散射使数据线一侧的n型半导体区域和p型半导体区域的杂质浓度比n型半导体区域和p型半导体区域的杂质浓度相对高于电容器。

55. 发明授权

US07235441B2 Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same 有权
标题翻译：具有锥形侧壁栅极的非易失性半导体存储器件及其制造方法
公开(公告)号：US07235441B2
公开(公告)日：2007-06-26
申请号：US10901347
申请日：2004-07-29
申请人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/4232 , H01L29/792
摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.
摘要翻译：在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

56. 发明申请

US20060022260A1 Semiconductor device and manufacturing method of semiconductor device 失效
公开(公告)号：US20060022260A1
公开(公告)日：2006-02-02
申请号：US11182013
申请日：2005-07-15
申请人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
发明人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0433 , H01L21/2815 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

57. 发明授权

US5374576A Method of fabricating stacked capacitor cell memory devices 失效
标题翻译：叠层电容器单元存储器件的制造方法
公开(公告)号：US5374576A
公开(公告)日：1994-12-20
申请号：US72482
申请日：1993-06-03
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

58. 发明授权

US5346834A Method for manufacturing a semiconductor device and a semiconductor memory device 失效
标题翻译：半导体装置及半导体存储装置的制造方法
公开(公告)号：US5346834A
公开(公告)日：1994-09-13
申请号：US845063
申请日：1992-03-03
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/265
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278 , Y10S148/014
摘要： An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.
摘要翻译：提供了一种用于制造绝缘栅场效应晶体管的改进方法。作为第一步骤，在硅衬底上生长氧化硅膜，并且在其上沉积第一氮化硅膜。然后使用抗蚀剂图案作为掩模来蚀刻第一硅亚硝酸盐膜，氧化硅膜和硅衬底，以形成包括硅衬底的至少一部分的硅岛。然后在通过第二步骤暴露的硅衬底的表面上以及在硅岛的表面上生长第二氧化硅膜，并且在其上沉积第二硅亚硝酸盐膜。然后蚀刻第二硅亚硝酸盐膜以留下沉积在硅岛的侧壁上的第二硅亚硝酸盐膜的一部分。之后，通过硅衬底的表面的热氧化生长第三氧化硅膜，以将硅岛与硅衬底电隔离。接下来，在硅岛上形成栅电极，随后在硅岛中形成源极和漏极区域，采用栅电极作为掩模。

59. 发明授权

US4670768A Complementary MOS integrated circuits having vertical channel FETs 失效
标题翻译：具有垂直沟道FET的互补MOS集成电路
公开(公告)号：US4670768A
公开(公告)日：1987-06-02
申请号：US767794
申请日：1985-08-14
申请人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
发明人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
IPC分类号： H01L27/08 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L27/02 , H01L27/12 , H01L29/06
CPC分类号： H01L29/7827 , H01L21/8221 , H01L21/823885 , H01L27/0688 , H01L27/092 , H01L27/1104 , H01L29/78642
摘要： A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.
摘要翻译： PCT No.PCT / JP84 / 00597 Sec。 371日期1985年8月14日 102（e）日期1985年8月14日PCT提交1984年12月14日PCT公布。第WO85 / 02716号公报日期：1985年6月20日。一种半导体集成电路，包括第一和第二突出极的形式的半导体区域，所述半导体区域设置在形成在半导体衬底或绝缘衬底上的半导体层上，并且具有绝缘设置在第一半导体区域中的p沟道FET，以及设置在第二半导体区域中的n沟道FET。这些FET在半导体区域的上部和底部具有源极和漏极区域，并且在半导体区域的侧面上具有栅极电极。突出的柱状半导体区域之间的绝缘区域被进一步用作栅极电极和栅极绝缘膜。

60. 发明申请

US20130051889A1 INPUT DEVICE 审中-公开
标题翻译：输入设备
公开(公告)号：US20130051889A1
公开(公告)日：2013-02-28
申请号：US13598131
申请日：2012-08-29
申请人： Shinichiro Kimura , Shinji Hirano
发明人： Shinichiro Kimura , Shinji Hirano
IPC分类号： B41J5/12
CPC分类号： G06F3/0338
摘要： An input device includes detection parts detecting operation from the outside, a cap member receiving operation from the outside, and an operation part including an operating shaft. The cap member is locked to one end of the operating shaft and a flange portion, which transmits the operation received from the outside, is formed at the other end of the operating shaft. The operating shaft includes an engaging hole formed at one end-side end face of the operating shaft. The cap member includes a first fitting portion having elasticity, and a protruding portion formed at the first fitting portion so as to protrude toward the outside of the cap member. The one end of the operating shaft is press-fitted to the first fitting portion and the protruding portion of the cap member is positioned in the engaging hole, so that the cap member is locked to the operation part.
摘要翻译：输入装置包括从外部检测操作的检测部件，从外部接收操作的帽部件和包括操作轴的操作部。盖构件被锁定到操作轴的一端，并且在操作轴的另一端形成有传递从外部接收的操作的凸缘部。操作轴包括形成在操作轴的一个端侧端面处的接合孔。盖构件包括具有弹性的第一装配部分和形成在第一装配部分上以朝向盖构件的外侧突出的突出部分。操作轴的一端被压配合到第一配合部分，并且帽构件的突出部分位于接合孔中，使得盖构件被锁定到操作部分。

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