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1. 发明授权

US4670768A Complementary MOS integrated circuits having vertical channel FETs 失效
标题翻译：具有垂直沟道FET的互补MOS集成电路
公开(公告)号：US4670768A
公开(公告)日：1987-06-02
申请号：US767794
申请日：1985-08-14
申请人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
发明人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
IPC分类号： H01L27/08 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L27/02 , H01L27/12 , H01L29/06
CPC分类号： H01L29/7827 , H01L21/8221 , H01L21/823885 , H01L27/0688 , H01L27/092 , H01L27/1104 , H01L29/78642
摘要： A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.
摘要翻译： PCT No.PCT / JP84 / 00597 Sec。 371日期1985年8月14日 102（e）日期1985年8月14日PCT提交1984年12月14日PCT公布。第WO85 / 02716号公报日期：1985年6月20日。一种半导体集成电路，包括第一和第二突出极的形式的半导体区域，所述半导体区域设置在形成在半导体衬底或绝缘衬底上的半导体层上，并且具有绝缘设置在第一半导体区域中的p沟道FET，以及设置在第二半导体区域中的n沟道FET。这些FET在半导体区域的上部和底部具有源极和漏极区域，并且在半导体区域的侧面上具有栅极电极。突出的柱状半导体区域之间的绝缘区域被进一步用作栅极电极和栅极绝缘膜。

2. 发明授权

US5012310A Semiconductor memory having stacked capacitor 失效
标题翻译：半导体存储器具有层叠电容
公开(公告)号：US5012310A
公开(公告)日：1991-04-30
申请号：US566315
申请日：1990-08-13
申请人： Shinichiro Kimura , Yoshifumi Kawamoto , Toru Kaga , Hideo Sunami
发明人： Shinichiro Kimura , Yoshifumi Kawamoto , Toru Kaga , Hideo Sunami
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10808
摘要： A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.
摘要翻译：公开了一种实现高集成度和高可靠性的兆比特动态随机存取存储器。消除了对制造堆叠式电容器存储单元进行的光掩模对准的允许的需要。每个存储单元的平板电极通过绝缘膜与存储器阵列中的对应数据线隔离，该绝缘膜自行设置在平板电极周围。

3. 发明授权

US4873203A Method for formation of insulation film on silicon buried in trench 失效
标题翻译：在埋在沟槽中的硅上形成绝缘膜的方法
公开(公告)号：US4873203A
公开(公告)日：1989-10-10
申请号：US221351
申请日：1988-07-19
申请人： Toru Kaga , Shinichiro Kimura , Tokuo Kure , Yoshifumi Kawamoto , Hideo Sunami
发明人： Toru Kaga , Shinichiro Kimura , Tokuo Kure , Yoshifumi Kawamoto , Hideo Sunami
IPC分类号： H01L27/04 , H01L21/316 , H01L21/32 , H01L21/334 , H01L21/763 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L29/66181 , H01L21/32 , H01L21/763
摘要： An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.
摘要翻译：通过使用在硅衬底上形成的第一Si 3 N 4掩模形成场氧化膜，形成用于形成沟槽的第二Si 3 N 4掩模，通过使用硅衬底形成硅衬底中的沟槽来制备掩埋在沟槽中的硅上的绝缘膜第二Si 3 N 4掩模，在沟槽中埋入多晶硅，除去第二Si 3 N 4掩模，同时留下第一Si 3 N 4掩模，并通过热氧化氧化掩埋在沟槽中的多晶硅的表面。埋在沟槽中的硅上如此形成的绝缘膜具有均匀的厚度和高介电强度。在将来将形成有源元件的部分处的基板的表面不被氧化。

4. 发明授权

US4742018A Process for producing memory cell having stacked capacitor 失效
标题翻译：具有层叠电容器的存储单元的制造方法
公开(公告)号：US4742018A
公开(公告)日：1988-05-03
申请号：US936602
申请日：1986-12-01
申请人： Shinichiro Kimura , Hideo Sunami
发明人： Shinichiro Kimura , Hideo Sunami
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , Y10S148/014
摘要： A process for producing a memory cell having a stacked capacitor. As the reduction in device size of memory cells progresses, it becomes difficult to obtain a satisfactorily large capacitance even with a stacked capacitor structure. To enable a larger capacitance to be obtained for the same occupied area, projections and recesses are provided on the surface of a capacitor electrode. It is possible, according to the process, to readily produce projections and recesses for increasing the storage capacitance.
摘要翻译：一种具有叠层电容器的存储单元的制造方法。随着存储器单元的器件尺寸的减小进行，即使堆叠的电容器结构也难以获得令人满意的大电容。为了能够为相同的占用面积获得更大的电容，在电容器电极的表面上设置有凹凸。根据该方法，可以容易地产生用于增加存储电容的凸起和凹槽。

5. 发明授权

US4918502A Semiconductor memory having trench capacitor formed with sheath electrode 失效
标题翻译：具有形成有护套电极的沟槽电容器的半导体存储器
公开(公告)号：US4918502A
公开(公告)日：1990-04-17
申请号：US123235
申请日：1987-11-20
申请人： Toru Kaga , Shinichiro Kimura , Hideo Sunami
发明人： Toru Kaga , Shinichiro Kimura , Hideo Sunami
IPC分类号： H01L27/108
CPC分类号： H01L27/10829
摘要： The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor formed within a substrate, and a switching transistor; one electrode of the capacitor having a sheath-shaped structure which is electrically continuous with the Si substrate at a bottom of a groove and whose sideward periphery is covered with an insulator, the other electrode of the capacitor having a part which is buried inside the sheath electrode and another part which is electrically connected with an impurity diffused layer to function as a source region of the transistor. Further, a structure in which a voltage of 1/2 V.sub.cc can be applied to a plate electrode of a memory cell having a trench capacitor is disclosed.
摘要翻译：本发明涉及高度封装的半导体存储器，更具体地说，涉及一种具有用于CMOS存储器的沟槽电容器的存储单元。本发明公开了一种半导体存储器，其采用由形成在衬底内的沟槽型电荷存储电容器构成的存储单元和开关晶体管; 电容器的一个电极具有鞘状结构，其在沟槽的底部与Si衬底电连接，并且其侧面被绝缘体覆盖，电容器的另一个电极具有埋在护套内的部分电极和与杂质扩散层电连接以用作晶体管的源极区的另一部分。此外，公开了可以向具有沟槽电容器的存储单元的板电极施加1/2Vcc的电压的结构。

6. 发明授权

US4873560A Dynamic random access memory having buried word lines 失效
标题翻译：具有掩埋字线的动态随机存取存储器
公开(公告)号：US4873560A
公开(公告)日：1989-10-10
申请号：US155698
申请日：1988-02-16
申请人： Hideo Sunami , Shinichiro Kimura , Toru Kaga
发明人： Hideo Sunami , Shinichiro Kimura , Toru Kaga
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10841 , Y10S257/922
摘要： This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.
摘要翻译：本发明涉及一种非常大规模的动态随机存取存储器，并且公开了一种在器件表面部分上具有减小的步长并且几乎不受入射放射线影响的存储单元。在由在半导体衬底中钻出的深孔组成的半导体存储器中，形成在深孔下半部分的侧壁部分上的电容器和形成在电容器上方的开关晶体管，至少形成一条字线的一半构成开关晶体管的栅极被埋在形成在半导体衬底的表面部分处的细长凹部中。

7. 发明授权

US4570175A Three-dimensional semiconductor device with thin film monocrystalline member contacting substrate at a plurality of locations 失效
标题翻译：具有薄膜单晶构件的三维半导体器件在多个位置处接触衬底
公开(公告)号：US4570175A
公开(公告)日：1986-02-11
申请号：US505377
申请日：1983-06-16
申请人： Masanobu Miyao , Makoto Ohkura , Iwao Takemoto , Terunori Warabisako , Kiichiro Mukai , Ryo Haruta , Yasushiro Nishioka , Shinichiro Kimura , Takashi Tokuyama
发明人： Masanobu Miyao , Makoto Ohkura , Iwao Takemoto , Terunori Warabisako , Kiichiro Mukai , Ryo Haruta , Yasushiro Nishioka , Shinichiro Kimura , Takashi Tokuyama
IPC分类号： H01L27/00 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78 , H01L29/786
CPC分类号： H01L21/76264 , H01L27/0688 , H01L21/76272 , H01L21/76281
摘要： At least one layer of insulator film and single-crystal film are alternately stacked and deposited on a surface of a semiconductor substrate, and an impurity-doped region formed in each semiconductor film is used as a gate, source or drain of a MOS transistor.Thus, a three-dimensional semiconductor device is constructed in which MOS transistors are arranged, not only in the direction of the semiconductor substrate surface, but also in a direction perpendicular thereto.
摘要翻译：绝缘膜和单晶膜的至少一层交替层叠并沉积在半导体衬底的表面上，并且将形成在每个半导体膜中的杂质掺杂区域用作MOS晶体管的栅极，源极或漏极。因此，不仅在半导体衬底表面的方向上，而且在垂直于其的方向上，构成了MOS晶体管被布置的三维半导体器件。

8. 发明申请

US20100232231A1 SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件
公开(公告)号：US20100232231A1
公开(公告)日：2010-09-16
申请号：US12787158
申请日：2010-05-25
申请人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh HISAMOTO , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译：提供一种稳定运行半导体非易失性存储器件的操作方案。当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。因此，可以验证擦除状态，而不知道任何时变变化。此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

9. 发明申请

US20100135080A1 FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US20100135080A1
公开(公告)日：2010-06-03
申请号：US12648796
申请日：2009-12-29
申请人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh HISAMOTO , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

10. 发明申请

US20100097246A1 INPUT DEVICE AND KEYBOARD DEVICE HAVING ILLUMINATION FUNCTION 失效
标题翻译：具有照明功能的输入设备和键盘设备
公开(公告)号：US20100097246A1
公开(公告)日：2010-04-22
申请号：US12579903
申请日：2009-10-15
申请人： Kazutoshi WATANABE , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
发明人： Kazutoshi WATANABE , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
IPC分类号： H03M11/00
CPC分类号： G06F3/0202 , H01H13/83 , H01H2219/044 , H01H2219/056 , H01H2219/06 , H01H2219/062
摘要： An input device includes a plurality of manipulation portions; an input function portion manipulated by the manipulation portions to perform an input function; a light guiding sheet facing the rear side of the plurality of manipulation portions; and a light source applying light into the light guiding sheet, wherein a rear surface opposite to a front surface of the light guiding sheet facing the manipulation portions is provided with a plurality of concave portions which is depressed to the inside of the light guiding sheet, wherein each concave portion has a circular opening and an inner surface which is a smooth concave curve surface, and wherein light propagated through the inside of the light guiding sheet is reflected by the inner surface toward the inside of the light guiding sheet, and the light is applied from the front surface of the light guiding sheet to the manipulation portions.
摘要翻译：输入装置包括多个操作部分; 由操作部分操纵以输入功能的输入功能部分; 面向所述多个操作部的后侧的导光片; 以及向所述导光片施加光的光源，其中与所述导光片的面对所述操作部的前表面相对的后表面设置有多个凹陷部，所述凹部被压向所述导光片的内部，其特征在于，每个凹部具有圆形开口和内表面，该内表面是光滑的凹曲面，并且其中通过导光片的内部传播的光被内表面朝向导光片的内部反射，并且光从导光片的前表面施加到操作部。

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