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51. 发明授权

US08171433B2 Method of calculating pattern-failure-occurrence-region, computer program product, pattern-layout evaluating method, and semiconductor-device manufacturing method 有权
标题翻译：计算图案故障发生区域，计算机程序产品，图案布局评估方法和半导体器件制造方法的方法
公开(公告)号：US08171433B2
公开(公告)日：2012-05-01
申请号：US12554495
申请日：2009-09-04
申请人： Masanori Takahashi , Toshiya Kotani , Satoshi Tanaka
发明人： Masanori Takahashi , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.
摘要翻译：计算图案故障发生区域的方法包括使用关系信息和用于形成凸部的布局来计算图案故障发生区域，所述关系信息是从胶片中形成的图案到覆盖凸起的距离之间的关系由于凸部的影响，形成图案的形状不能满足规定条件的膜中的与凸部的基板上的区域。

52. 发明授权

US07934175B2 Parameter adjustment method, semiconductor device manufacturing method, and recording medium 有权
标题翻译：参数调整方法，半导体器件制造方法和记录介质
公开(公告)号：US07934175B2
公开(公告)日：2011-04-26
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.
摘要翻译：用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。

53. 发明授权

US07794897B2 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 失效
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US07794897B2
公开(公告)日：2010-09-14
申请号：US11068896
申请日：2005-03-02
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

54. 发明申请

US20090265680A1 Method and system for correcting a mask pattern design 失效
标题翻译：用于校正掩模图案设计的方法和系统
公开(公告)号：US20090265680A1
公开(公告)日：2009-10-22
申请号：US12457751
申请日：2009-06-19
申请人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
发明人： Kyoko Izuha , Shigeki Nojima , Toshiya Kotani , Satoshi Tanaka
IPC分类号： G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A pattern verification method comprising preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges, the positional displacement being displacement between first point and the evaluation point, computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.
摘要翻译：一种图案验证方法，包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个工艺参数以计算所转印/形成的图案，定义对于每个过程参数的参考值和可变范围，计算与评估点相对应的每个第一点的位置位移，使用校正掩模图案计算的第一点和通过改变其中的处理参数而获得的参数值的多个组合可变范围或在各个可变范围内，位置偏移是第一点和评估点之间的位移，计算每个评估点的位置偏移的统计，以及根据统计信息输出修改掩模图案的信息。

55. 发明申请

US20090186429A1 Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device 失效
标题翻译：用于校正掩模图案的方法，用于校正掩模图案的系统，程序，用于制造光掩模的方法和用于制造半导体器件的方法
公开(公告)号：US20090186429A1
公开(公告)日：2009-07-23
申请号：US12379047
申请日：2009-02-11
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： H01L21/66 , G06F17/50
CPC分类号： G03F7/70441 , G03F1/36
摘要： A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value.
摘要翻译：用于校正掩模图案的计算机实现方法包括：通过使用掩模图案来预测设备图案的位移以形成设备图案和处理条件的变化; 确定光学接近校正值，使得位移落在器件图案的位移公差内; 以及使用光学接近校正值来校正掩模图案。

56. 发明授权

US07560197B2 Mask pattern data producing method, patterning method, reticle correcting method, reticle manufacturing method, and semiconductor apparatus manufacturing method 失效
标题翻译：掩模图案数据制作方法，图案形成方法，掩模版修正方法，掩模版制造方法和半导体装置的制造方法
公开(公告)号：US07560197B2
公开(公告)日：2009-07-14
申请号：US11061599
申请日：2005-02-22
申请人： Hiroko Nakamura , Toshiya Kotani , Satoshi Tanaka , Shoji Mimotogi
发明人： Hiroko Nakamura , Toshiya Kotani , Satoshi Tanaka , Shoji Mimotogi
IPC分类号： G03F1/06
CPC分类号： G03F7/0035 , G03F1/92 , G03F7/40
摘要： A mask pattern data producing method is disclosed, which comprises preparing design pattern data in which contact holes are arranged on part of the grid points in matrix, preparing first mask pattern data in which first opening patterns are arranged on all of the grid points, and designing second mask pattern data in which second opening patterns and third opening patterns are arranged, the second opening patterns being arranged on the grid points at which the contact holes are arranged in the design pattern data to include the first opening patterns, the third opening patterns being arranged on a pair of grid points, which is a pair of diagonal grid points only on which the contact holes are arranged in a unit grid formed by four grid points, to include the first opening patterns arranged on the pair of grid points, in place of the second opening patterns.
摘要翻译：公开了一种掩模图案数据制作方法，其特征在于，准备设置图形数据，其中接触孔被布置在矩阵中的网格点的一部分上，准备在所有网格点上布置第一开口图案的第一掩模图案数据，以及设计其中布置有第二开口图案和第三开口图案的第二掩模图案数据，第二开口图案布置在布置在设计图案数据中的接触孔的网格点上以包括第一开口图案，第三开口图案布置在一对栅格点上，该对栅格点仅在其上以4个格栅点形成的单位格栅布置在其上，以包括布置在该对网格点上的第一开口图案，第二个打开模式的地方。

57. 发明授权

US07526748B2 Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium 失效
标题翻译：设计图案数据准备方法，掩模图案数据准备方法，掩模制造方法，半导体器件制造方法和程序记录介质
公开(公告)号：US07526748B2
公开(公告)日：2009-04-28
申请号：US11200176
申请日：2005-08-10
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： H01J37/3026 , G03F1/36 , G03F1/68
摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.
摘要翻译：一种设计图案数据准备方法，包括基于第一设计图案数据准备第一掩模图案数据，基于第一掩模图案数据预测在与第一掩模图案相对应的晶片上形成的晶片图案，判断是否存在有限差在预定的晶片图案和要在晶片上形成的图案之间的预定容许变化量在预定的允许变化量中，选择性地校正第一设计图案数据的一部分，当有限差不在内部时，包括对应于有限差的部分通过合成对应于包括选择性校正的部分的部分的第一掩模图案数据和通过消除与包括从第一掩模选择性校正的部分相对应的部分的第一掩模图案数据而获得的数据来准备第二设计图案数据模式数据。

58. 发明授权

US07482661B2 Pattern forming method and semiconductor device manufactured by using said pattern forming method 有权
标题翻译：图案形成方法和使用所述图案形成方法制造的半导体器件
公开(公告)号：US07482661B2
公开(公告)日：2009-01-27
申请号：US11119810
申请日：2005-05-03
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： H01L27/088
CPC分类号： G03F1/36 , Y10S438/926
摘要： A pattern forming method includes determining an allowable value of an etching conversion difference, obtaining a maximum distance between patterns generating the etching conversion difference within the allowable value, the patterns including main patterns or both main patterns and a dummy pattern, preparing a first design layout in which a first distance between the main patterns is smaller than the maximum distance, or a second design layout in which a second distance between the main patterns and the dummy pattern is smaller than the maximum distance, performing a design data conversion based on the first or second design layout to form first or second design data, and forming the main patterns by using the first design data, or forming both the main patterns and the dummy pattern by using the second design data.
摘要翻译：图案形成方法包括：确定蚀刻转换差的允许值，获得在允许值内产生蚀刻转换差的图案之间的最大距离，包括主图案或两个主图案和虚设图案的图案，准备第一设计布局或者主图案与虚拟图案之间的第二距离小于最大距离的第二设计布局，其中基于第一图案进行设计数据转换，其中，主图案之间的第一距离小于最大距离，或第二设计布局以形成第一或第二设计数据，以及通过使用第一设计数据形成主图案，或者通过使用第二设计数据形成主图案和伪图案。

59. 发明申请

US20080250381A1 PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM 有权
标题翻译：参数调整方法，半导体器件制造方法和记录介质
公开(公告)号：US20080250381A1
公开(公告)日：2008-10-09
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation.
摘要翻译：用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整作为参考制造装置的制造装置可调节的参数，使其落在预定的允许变化并将调整参数定义为参考制造装置的参考参数; 使用参考制造装置从掩模获得要在基板上形成的半导体器件的图案的第一形状，以在将参考参数设置为参考制造装置并将所获得的第一形状定义为参考完成形状; 将另一个待调节制造装置的可调参数定义为待调整制造装置的待调整参数; 当将所述规定的待调整参数设定为所述待调节制造装置并且将所获得的第二形状定义为所述第二形状时，从所述掩模获得使用所述待调节制造装置在所述基板上形成的所述图案的第二形状一个待调整的成品形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 作为待调整制造装置的参数输出具有等于或小于预定参考值的差值的待调整参数或具有等于或等于或等于或等于通过重复计算小于预定的参考值。

60. 发明申请

US20070003127A1 Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method 失效
标题翻译：半导体器件图案生成方法，图案数据处理方法，图案数据处理程序和半导体器件制造方法
公开(公告)号：US20070003127A1
公开(公告)日：2007-01-04
申请号：US11474297
申请日：2006-06-26
申请人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
发明人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
IPC分类号： G06K9/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.
摘要翻译：从包含半导体集成电路的图案的第一设计数据中提取尺寸不大于阈值的校正对象图案。基于第一设计数据计算半导体集成电路的第一特性。通过校正包含在第一设计数据中的校正目标图案来生成第二设计数据。基于第二设计数据计算半导体集成电路的第二特性。检查第一特性和第二特性之间的特性差是否落在公差之内。当特性差在公差范围内时，决定使用第二设计数据来制造半导体集成电路。

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