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1. 发明授权

US07934175B2 Parameter adjustment method, semiconductor device manufacturing method, and recording medium 有权
标题翻译：参数调整方法，半导体器件制造方法和记录介质
公开(公告)号：US07934175B2
公开(公告)日：2011-04-26
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya Kotani , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate; defining an adjustable parameter of another to-be-adjusted manufacturing; obtaining a second shape of the pattern formed on the substrate; calculating a difference amount between a reference finished shape and a to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; and outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter.
摘要翻译：用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整可用于作为参考制造装置的制造装置的参数; 获得要在基板上形成的半导体器件的图案的第一形状; 定义另一个待调整制造的可调参数; 获得形成在所述基板上的所述图案的第二形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 并作为待调整制造装置的参数输出待调整参数。

2. 发明申请

US20080250381A1 PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM 有权
标题翻译：参数调整方法，半导体器件制造方法和记录介质
公开(公告)号：US20080250381A1
公开(公告)日：2008-10-09
申请号：US12062859
申请日：2008-04-04
申请人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
发明人： Toshiya KOTANI , Yasunobu Kai , Soichi Inoue , Satoshi Tanaka , Shigeki Nojima , Kazuyuki Masukawa , Koji Hashimoto
IPC分类号： G06F17/50
CPC分类号： G03F7/70625 , G03F7/70525 , H01L22/12 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation.
摘要翻译：用于使用该制造装置在基板上形成半导体器件的图案的多个制造装置的参数调整方法包括：调整作为参考制造装置的制造装置可调节的参数，使其落在预定的允许变化并将调整参数定义为参考制造装置的参考参数; 使用参考制造装置从掩模获得要在基板上形成的半导体器件的图案的第一形状，以在将参考参数设置为参考制造装置并将所获得的第一形状定义为参考完成形状; 将另一个待调节制造装置的可调参数定义为待调整制造装置的待调整参数; 当将所述规定的待调整参数设定为所述待调节制造装置并且将所获得的第二形状定义为所述第二形状时，从所述掩模获得使用所述待调节制造装置在所述基板上形成的所述图案的第二形状一个待调整的成品形状; 计算参考完成形状和待调整完成形状之间的差值; 通过改变待调整参数重复计算差值，直到差值变得等于或小于预定参考值; 作为待调整制造装置的参数输出具有等于或小于预定参考值的差值的待调整参数或具有等于或等于或等于或等于通过重复计算小于预定的参考值。

3. 发明申请

US20050250022A1 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 失效
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US20050250022A1
公开(公告)日：2005-11-10
申请号：US11068896
申请日：2005-03-02
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03C5/00 , G03F1/14 , G03F9/00 , G06F17/50 , G06K9/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

4. 发明授权

US08142961B2 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 有权
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US08142961B2
公开(公告)日：2012-03-27
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

5. 发明申请

US20100159709A1 MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：掩模图像校正方法，掩模图案检查方法，照相胶片制造方法和半导体器件制造方法
公开(公告)号：US20100159709A1
公开(公告)日：2010-06-24
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： H01L21/302 , G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

6. 发明授权

US07090949B2 Method of manufacturing a photo mask and method of manufacturing a semiconductor device 有权
标题翻译：制造光掩模的方法和制造半导体器件的方法
公开(公告)号：US07090949B2
公开(公告)日：2006-08-15
申请号：US10724738
申请日：2003-12-02
申请人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
发明人： Shigeki Nojima , Shoji Mimotogi , Satoshi Tanaka , Toshiya Kotani , Shigeru Hasebe , Koji Hashimoto , Soichi Inoue , Osamu Ikenaga
IPC分类号： G01F9/00
CPC分类号： G03F1/36 , G03F1/68
摘要： Disclosed is a method of manufacturing a photo mask comprising preparing mask data for a mask pattern to be formed on a mask substrate, calculating edge moving sensitivity with respect to each of patterns included in the mask pattern using the mask data, the edge moving sensitivity corresponding to a difference between a proper exposure dose and an exposure dose to be set when a pattern edge varies, determining a monitor portion of the mask pattern, based on the calculated edge moving sensitivity, actually forming the mask pattern on the mask substrate, acquiring a dimension of a pattern included in that portion of the mask pattern formed on the mask substrate which corresponds to the monitor portion, determining evaluation value for the mask pattern formed on the mask substrate, based on the acquired dimension, and determining whether the evaluation value satisfies predetermined conditions.
摘要翻译：公开了一种制造光掩模的方法，其包括：对掩模基板上形成的掩模图案准备掩模数据，使用掩模数据计算相对于包含在掩模图案中的每个图案的边缘移动灵敏度，边缘移动灵敏度对应对于在图案边缘变化时要设置的适当曝光剂量和曝光剂量之间的差异，基于计算出的边缘移动灵敏度确定掩模图案的监视部分，实际在掩模基板上形成掩模图案，获取基于所获取的尺寸，确定在掩模基板上形成的掩模图案的评估值，并且确定评估值是否满足的掩模图案的形成在掩模基板上的对应于监视部分的掩模图案的部分中的图案的尺寸预定条件。

7. 发明授权

US07794897B2 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 失效
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US07794897B2
公开(公告)日：2010-09-14
申请号：US11068896
申请日：2005-03-02
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

8. 发明申请

US20060033049A1 Design pattern data preparing method, mask pattern data preparing method, mask manufacturing method, semiconductor device manufacturing method, and program recording medium 失效
公开(公告)号：US20060033049A1
公开(公告)日：2006-02-16
申请号：US11200176
申请日：2005-08-10
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Soichi Inoue
IPC分类号： G21K5/10
CPC分类号： H01J37/3026 , G03F1/36 , G03F1/68
摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.

9. 发明授权

US07194704B2 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US07194704B2
公开(公告)日：2007-03-20
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

10. 发明申请

US20050204322A1 Design layout preparing method 有权
标题翻译：设计布局准备方法
公开(公告)号：US20050204322A1
公开(公告)日：2005-09-15
申请号：US11012491
申请日：2004-12-16
申请人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
发明人： Toshiya Kotani , Shigeki Nojima , Suigen Kyoh , Kyoko Izuha , Ryuji Ogawa , Satoshi Tanaka , Soichi Inoue , Hirotaka Ichikawa
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , G06F17/50 , H01L21/027 , H01L21/82
CPC分类号： G06F17/5081 , H01L21/0271
摘要： There is disclosed a method of producing a design layout by optimizing at least one of design rule, process proximity correction parameter and process parameter, including calculating a processed pattern shape based on a design layout and a process parameter, extracting a dangerous spot having an evaluation value with respect to the processed pattern shape, which does not satisfy a predetermined tolerance, generating a repair guideline of the design layout based on a pattern included in the dangerous spot, and repairing that portion of the design layout which corresponds to the dangerous spot based on the repair guideline.
摘要翻译：公开了一种通过优化设计规则，过程接近校正参数和过程参数中的至少一个来生成设计布局的方法，包括基于设计布局和过程参数来计算处理的图案形状，提取具有评估的危险点相对于不满足预定公差的加工图案形状的值，基于包含在危险点中的图案生成设计布局的修理指南，并且修复与危险点对应的设计布局的那部分在维修准则上。

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