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51. 发明授权

US4383885A Reactive sputter etching of polysilicon utilizing a chlorine etch gas 失效
标题翻译：使用氯气气体对多晶硅进行反应溅射蚀刻
公开(公告)号：US4383885A
公开(公告)日：1983-05-17
申请号：US300307
申请日：1981-09-08
申请人： Dan Maydan , David N. Wang
发明人： Dan Maydan , David N. Wang
IPC分类号： C04B41/53 , H01L21/3065 , H01L21/3213 , H01L21/308
CPC分类号： C04B41/5346 , H01L21/3065 , H01L21/32137
摘要： In a chlorine plasma, reactive sputter etching of monocrystalline silicon, undoped polycrystalline silicon or doped polycrystalline silicon is achieved. The etching processes are substantially free of any loading effects and are characterized by high resolution, excellent uniformity and high selectivity with respect to, for example, silicon dioxide. For silicon and undoped polysilicon, the edge profile of the etched material is anisotropic. For doped polysilicon, the edge profile can be controlled to occur anywhere in the range from completely isotropic to completely anisotropic.
摘要翻译：在氯等离子体中，实现了单晶硅，未掺杂多晶硅或掺杂多晶硅的反应溅射蚀刻。蚀刻工艺基本上没有任何负载效应，其特征在于相对于例如二氧化硅的高分辨率，优异的均匀性和高选择性。对于硅和未掺杂的多晶硅，蚀刻材料的边缘轮廓是各向异性的。对于掺杂多晶硅，可以将边缘轮廓控制在从完全各向同性到完全各向异性的范围内的任何地方。

52. 发明申请

US20060223233A1 Apparatus and method for heating substrates 失效
公开(公告)号：US20060223233A1
公开(公告)日：2006-10-05
申请号：US11445630
申请日：2006-06-02
申请人： Jun Zhao , David Quach , Timothy Weidman , Rick Roberts , Farhad Moghadam , Dan Maydan
发明人： Jun Zhao , David Quach , Timothy Weidman , Rick Roberts , Farhad Moghadam , Dan Maydan
IPC分类号： H01L21/00 , F28F7/00
CPC分类号： H01L21/67109 , Y10S414/139
摘要： An apparatus for processing substrates is disclosed. In one embodiment, the apparatus includes a housing and a plurality of stacked cell structures in the housing. An actuator is adapted to move the plurality of stacked cell structures inside of the housing while substrates in the stacked cell structures are being heated.

53. 发明申请

US20050115921A1 OPTICAL INTEGRATED CIRCUITS (ICS) 有权
标题翻译：光集成电路（ICS）
公开(公告)号：US20050115921A1
公开(公告)日：2005-06-02
申请号：US09734950
申请日：2000-12-11
申请人： Cecilia Mak , John White , Kam Law , Dan Maydan
发明人： Cecilia Mak , John White , Kam Law , Dan Maydan
IPC分类号： G02B6/12 , G02B6/13 , G02B6/132 , B29D11/00
CPC分类号： G02B6/12004 , G02B6/13 , G02B6/132
摘要： In one aspect, the invention provides methods and apparatus for forming optical devices on large area substrates. The large area substrates are preferably made of quartz, silica or fused silica. The large area substrates enable larger optical devices to be formed on a single die. In another aspect, the invention provides methods and apparatus for forming integrated optical devices on large area substrates, such as quartz, silica or fused silica substrates. In another aspect, the invention provides methods and apparatus for forming optical devices using damascene techniques on large area substrates or silicon substrates. In another aspect, methods for forming optical devices by bonding an upper cladding layer on a lower cladding and a core is provided.
摘要翻译：一方面，本发明提供了用于在大面积基板上形成光学装置的方法和装置。大面积基板优选由石英，二氧化硅或熔融二氧化硅制成。大面积基板使得能够在单个管芯上形成更大的光学器件。另一方面，本发明提供了用于在大面积衬底（例如石英，二氧化硅或熔融二氧化硅衬底）上形成集成光学器件的方法和装置。在另一方面，本发明提供了使用大面积衬底或硅衬底上的镶嵌技术形成光学器件的方法和装置。在另一方面，提供了通过将下包层和芯上的上包层结合来形成光器件的方法。

54. 发明授权

US06869838B2 Deposition of passivation layers for active matrix liquid crystal display (AMLCD) applications 失效
标题翻译：沉积有源矩阵液晶显示（AMLCD）应用的钝化层
公开(公告)号：US06869838B2
公开(公告)日：2005-03-22
申请号：US10118864
申请日：2002-04-09
申请人： Kam Law , Quanyuan Shang , William Reid Harshbarger , Dan Maydan
发明人： Kam Law , Quanyuan Shang , William Reid Harshbarger , Dan Maydan
IPC分类号： H01L21/336 , H01L27/10
CPC分类号： H01L29/66757 , H01L29/66765 , H01L2924/0002 , H01L2924/00
摘要： A method of passivation layer deposition using a cyclical deposition process is described. The cyclical deposition process may comprise alternately adsorbing a silicon-containing precursor and a reactant gas on a substrate structure. Thin film transistors, such as a bottom-gate transistor or a top-gate transistor, including a silicon-containing passivation layer, may be formed using such cyclical deposition techniques.
摘要翻译：描述了使用循环沉积工艺的钝化层沉积的方法。循环沉积工艺可以包括在衬底结构上交替地吸附含硅前体和反应气体。可以使用这种循环沉积技术来形成包括含硅钝化层的诸如底栅晶体管或顶栅晶体管的薄膜晶体管。

55. 发明授权

US06576110B2 Coated anode apparatus and associated method 失效
公开(公告)号：US06576110B2
公开(公告)日：2003-06-10
申请号：US09797040
申请日：2001-02-28
申请人： Dan Maydan
发明人： Dan Maydan
IPC分类号： C25D500
CPC分类号： C25D7/123 , C25D17/001 , C25D17/10
摘要： An anode is configured to be used within a metal film plating apparatus. The anode has a substantially planar electric field generating portion and an electrolyte solution chemical reaction portion. The planar electric field generating portion is coated with an inert material that is impervious to the electrolyte solution. In one embodiment, the anode is formed as a perforated anode. In one aspect, the electric field generating portion is formed contiguous with the electrolyte solution chemical reaction portion. In another aspects, the planar electric field generating portion is formed as a distinct member from the electrolyte solution chemical reaction portion.

56. 发明授权

US06444277B1 Method for depositing amorphous silicon thin films onto large area glass substrates by chemical vapor deposition at high deposition rates 失效
标题翻译：通过化学气相沉积在高沉积速率下将非晶硅薄膜沉积到大面积玻璃基板上的方法
公开(公告)号：US06444277B1
公开(公告)日：2002-09-03
申请号：US08303566
申请日：1994-09-09
申请人： Kam S. Law , Robert Robertson , Pamela Lou , Marc Michael Kollrack , Angela Lee , Dan Maydan
发明人： Kam S. Law , Robert Robertson , Pamela Lou , Marc Michael Kollrack , Angela Lee , Dan Maydan
IPC分类号： B05D306
CPC分类号： C23C16/0245 , C23C16/24 , C23C16/4583 , C23C16/5096 , H01L21/02422 , H01L21/0245 , H01L21/02532 , H01L21/0262
摘要： Amorphous silicon thin films can be deposited onto large area glass substrates at high deposition rates by chemical vapor deposition using pressure of at least 0.8 Torr and temperatures of about 270-350° C. and fairly high gas flow rates of silane in a hydrogen carrier gas. The spacing between the inlet gas manifold and the substrate in the CVD chamber is maintained so as to maximize the deposition rate. Improved transistor characteristics are observed when the substrate is either exposed to a hydrogen plasma for a few seconds prior to high rate deposition of the amorphous silicon, or when a first layer of amorphous silicon is deposited using a slow deposition rate process prior to deposition of the high deposition rate amorphous silicon.
摘要翻译：非晶硅薄膜可以通过使用至少0.8托的压力和约270-350℃的温度的化学气相沉积以高沉积速率沉积到大面积玻璃基板上，并且在氢载气中具有相当高的硅烷气体流速。保持入口气体歧管和CVD室中的衬底之间的间隔，以使沉积速率最大化。当在非晶硅的高速沉积之前衬底被暴露于氢等离子体几秒钟时，或者当沉积第一层非晶硅之前使用缓慢沉积速率工艺沉积第一层非晶硅时，可以观察到改善的晶体管特性高沉积速率非晶硅。

57. 发明授权

US06414834B1 Dielectric covered electrostatic chuck 有权
标题翻译：介质覆盖静电卡盘
公开(公告)号：US06414834B1
公开(公告)日：2002-07-02
申请号：US09596108
申请日：2000-06-16
申请人： Edwin C. Weldon , Kenneth S. Collins , Arik Donde , Brian Lue , Dan Maydan , Robert J. Steger , Timothy Dyer , Ananda H. Kumar , Alexander M. Veytser , Kadthala R. Narendrnath , Semyon L. Kats , Arnold Kholodenko , Shamouil Shamouilian , Dennis S. Grimard
发明人： Edwin C. Weldon , Kenneth S. Collins , Arik Donde , Brian Lue , Dan Maydan , Robert J. Steger , Timothy Dyer , Ananda H. Kumar , Alexander M. Veytser , Kadthala R. Narendrnath , Semyon L. Kats , Arnold Kholodenko , Shamouil Shamouilian , Dennis S. Grimard
IPC分类号： H02N1300
CPC分类号： H01J37/321 , C23C16/4586 , H01J2237/2001 , H01L21/6831 , H01L21/6833 , Y10T279/23
摘要： An electrostatic chuck 100 useful for holding a substrate 55 in a high density plasma, comprises an electrode 110 at least partially covered by a semiconducting dielectric 115, wherein the semiconducting dielectric 115 may have an electrical resistance of from about 5×109 &OHgr;cm to about 8×1010 &OHgr;cm.
摘要翻译：用于将衬底55保持在高密度等离子体中的静电卡盘100包括至少部分被半导体电介质115覆盖的电极110，其中半导体电介质115可具有约5×10 9欧姆到约8×10 10欧姆·厘米的电阻。

58. 发明授权

US06372633B1 Method and apparatus for forming metal interconnects 失效
标题翻译：用于形成金属互连的方法和装置
公开(公告)号：US06372633B1
公开(公告)日：2002-04-16
申请号：US09111657
申请日：1998-07-08
申请人： Dan Maydan , Ashok K. Sinha , Zheng Xu , Liang-Yu Chen , Roderick Craig Mosely , Daniel Carl , Diana Xiaobing Ma , Yan Ye , Wen Chiang Tu
发明人： Dan Maydan , Ashok K. Sinha , Zheng Xu , Liang-Yu Chen , Roderick Craig Mosely , Daniel Carl , Diana Xiaobing Ma , Yan Ye , Wen Chiang Tu
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/32136 , H01L21/76885
摘要： The present invention provides a method and apparatus for forming reliable interconnects in which the overlap of the line over the plug or via is minimized or eliminated. In one aspect, a barrier plug comprised of a conductive material, such as tungsten, is deposited over the via to provide an etch stop during line etching and to prevent diffusion of the metal, such as copper, into the surrounding dielectric material if the line is misaligned over the via. Additionally, the barrier plug prevents an overall reduction in resistance of the interconnect and enables reactive ion etching to be employed to form the metal line. In another aspect, reactive ion etching techniques are employed to selectively etch the metal line and the barrier layer to provide a controlled etching process which exhibits selectivity for the metal line, then the barrier and then the via or plug.
摘要翻译：本发明提供了一种用于形成可靠互连的方法和装置，其中使插塞或通孔上的线重叠最小化或消除。在一个方面，由诸如钨的导电材料构成的阻挡塞沉积在通孔上，以在线蚀刻期间提供蚀刻停止并且防止金属（例如铜）扩散到周围的介电材料中，如果线在通道上不对齐。此外，阻挡塞防止互连的电阻的总体降低，并且能够使用反应离子蚀刻来形成金属线。在另一方面，使用反应离子蚀刻技术来选择性地蚀刻金属线和阻挡层，以提供对金属线，然后是屏障，然后是通孔或插塞的选择性的受控蚀刻工艺。

59. 发明授权

US06170428B2 Symmetric tunable inductively coupled HDP-CVD reactor 失效
标题翻译：对称可调谐电感耦合HDP-CVD反应堆
公开(公告)号：US06170428B2
公开(公告)日：2001-01-09
申请号：US08679927
申请日：1996-07-15
申请人： Fred C. Redeker , Farhad Moghadam , Hiroji Hanawa , Tetsuya Ishikawa , Dan Maydan , Shijian Li , Brian Lue , Robert J. Steger , Manus Wong , Yaxin Wong , Ashok K. Sinha
发明人： Fred C. Redeker , Farhad Moghadam , Hiroji Hanawa , Tetsuya Ishikawa , Dan Maydan , Shijian Li , Brian Lue , Robert J. Steger , Manus Wong , Yaxin Wong , Ashok K. Sinha
IPC分类号： C23C1600
CPC分类号： H01J37/32449 , C23C16/507 , H01J37/321 , H01J37/32467 , H01J37/32522 , H01J37/32862
摘要： The present invention provides an HDP-CVD tool using simultaneous deposition and sputtering of doped and undoped silicon dioxide capable of excellent gap fill and blanket film deposition on wafers having sub 0.5 micron feature sizes having aspect ratios higher than 1.2:1. The system of the present invention includes: a dual RF zone inductively coupled plasma source configuration capable of producing radially tunable ion currents across the wafer; a dual zone gas distribution system to provide uniform deposition properties across the wafer surface; temperature controlled surfaces to improve film adhesion and to control extraneous particle generation; a symmetrically shaped turbomolecular pumped chamber body to eliminate gas flow or plasma ground azimuthal asymmetries; a dual helium cooling zone electrostatic chuck to provide and maintain uniform wafer temperature during processing; an all ceramic/aluminum alloy chamber construction to eliminate chamber consumables; and a remote fluorine based plasma chamber cleaning system for high chamber cleaning rate without chuck cover plates.
摘要翻译：本发明提供一种使用同时沉积和溅射掺杂和未掺杂的二氧化硅的HDP-CVD工具，其能够在具有高于1.2:1的纵横比的0.5微米特征尺寸的晶片上具有优异的间隙填充和覆盖膜沉积。本发明的系统包括：双RF区电感耦合等离子体源配置，其能够跨晶片产生径向可调离子电流; 双区气体分配系统，以在晶片表面上提供均匀的沉积性能; 温度控制表面，以改善膜的附着力并控制外来颗粒的产生; 一个对称成形的涡轮分子抽吸室体，以消除气体流动或等离子体地面方位不对称性; 双氦冷却区静电卡盘，在加工过程中提供并保持晶圆温度均匀; 全陶瓷/铝合金室结构，可消除室内耗材; 以及远程氟基等离子体室清洁系统，用于无卡盘盖板的高室清洁率。

60. 发明授权

US06167834A Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process 失效
公开(公告)号：US06167834A
公开(公告)日：2001-01-02
申请号：US07928642
申请日：1992-08-13
申请人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
发明人： David Nin-Kou Wang , John M. White , Kam S. Law , Cissy Leung , Salvador P. Umotoy , Kenneth S. Collins , John A. Adamik , Ilya Perlov , Dan Maydan
IPC分类号： C23C1600
CPC分类号： C23C16/45565 , C23C16/402 , C23C16/455 , C23C16/45521 , C23C16/5096 , C23C16/54 , H01J37/32082 , H01J37/3244 , H01L21/31604
摘要： A high pressure, high throughput, single wafer, semiconductor processing reactor is disclosed which is capable of thermal CVD, plasma-enhanced CVD, plasma-assisted etchback, plasma self-cleaning, and deposition topography modification by sputtering, either separately or as part of in-situ multiple step processing. The reactor includes cooperating arrays of interdigitated susceptor and wafer support fingers which collectively remove the wafer from a robot transfer blade and position the wafer with variable, controlled, close parallel spacing between the wafer and the chamber gas inlet manifold, then return the wafer to the blade. A combined RF/gas feed-through device protects against process gas leaks and applies RF energy to the gas inlet manifold without internal breakdown or deposition of the gas. The gas inlet manifold is adapted for providing uniform gas flow over the wafer. Temperature-controlled internal and external manifold surfaces suppress condensation, premature reactions and decomposition and deposition on the external surfaces. The reactor also incorporates a uniform radial pumping gas system which enables uniform reactant gas flow across the wafer and directs purge gas flow downwardly and upwardly toward the periphery of the wafer for sweeping exhaust gases radially away from the wafer to prevent deposition outside the wafer and keep the chamber clean. The reactor provides uniform processing over a wide range of pressures including very high pressures. A low temperature CVD process for forming a highly conformal layer of silicon dioxide is also disclosed. The process uses very high chamber pressure and low temperature, the TEOS and ozone reactants. The low temperature CVD silicon dioxide deposition step is particularly useful for planarizing underlying stepped dielectric layers, either alone or in conjunction with a subsequent isotropic etch. A preferred in-situ multiple-step process for forming a planarized silicon dioxide layer uses (1) high rate silicon dioxide deposition at a low temperature and high pressure followed by (2) the deposition of the conformal silicon dioxide layer also at high pressure and low temperature, followed by (3) a high rate isotropic etch, preferably at low temperature and high pressure in the same reactor used for the two oxide deposition steps. Various combinations of the steps are disclosed for different applications, as is a preferred reactor self-cleaning step.

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