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51. 发明授权

US5065225A Tunneling diffusion barrier for local interconnect and polysilicon high impedance device 失效
标题翻译：用于局部互连和多晶硅高阻抗器件的隧道扩散势垒
公开(公告)号：US5065225A
公开(公告)日：1991-11-12
申请号：US560384
申请日：1990-07-31
申请人： Frank R. Bryant , John L. Walters
发明人： Frank R. Bryant , John L. Walters
IPC分类号： H01L23/532
CPC分类号： H01L23/5329 , H01L23/53271 , H01L2924/0002 , H01L2924/3011
摘要： A semiconductor device is described in which a conductive layer overlaps a dielectric layer forming a composite electrical device deposited over selected portions of a semiconductor substrate chemically isolating the conductive layer portion of the composite electrical device from the substrate, thereby preventing difffusion of dopant material through the dielectric layer into and out of the conductive layer while simultaneously allowing for tunneling of electrons through the dielectric layer to and from the conductive layer and the semiconductor substrate.
摘要翻译：描述了一种半导体器件，其中导电层与形成复合电器件的电介质层重叠，沉积在半导体衬底的选定部分上，从而将复合电器件的导电层部分与衬底化学隔离，从而防止掺杂剂材料通过介电层进出导电层，同时允许电子穿过电介质层穿过导电层和半导体衬底穿过电介质层。

52. 发明授权

US07543917B2 Integrated circuit and method for manufacturing 有权
标题翻译：集成电路及制造方法
公开(公告)号：US07543917B2
公开(公告)日：2009-06-09
申请号：US11540321
申请日：2006-09-29
申请人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
发明人： Simon Dodd , S. Jonathan Wang , Dennis W. Tom , Frank R. Bryant , Terry E. McMahon , Richard Todd Miller , Gregory T. Hindman
IPC分类号： B41J2/05
CPC分类号： B41J2/1628 , B41J2/14129 , B41J2/1603 , B41J2202/13 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a semiconductor device, the method including forming a substrate including a first surface having a non-doped region, forming an insulative material over the first surface of the substrate, forming a first conductive material over the first insulative material, forming an opening in the first conductive material that forms a path to the substrate that is substantially free of the first conductive material and the first insulative material, forming a second insulative material over the first conductive material, and forming a second conductive material over the second insulative material, wherein the second conductive material is formed in the opening and contacts the non-doped region of the substrate.
摘要翻译：一种形成半导体器件的方法，所述方法包括形成包括具有非掺杂区域的第一表面的衬底，在所述衬底的第一表面上形成绝缘材料，在所述第一绝缘材料上形成第一导电材料，形成第在所述第一导电材料中开口，所述第一导电材料形成基本上不含所述第一导电材料和所述第一绝缘材料的路径，在所述第一导电材料上形成第二绝缘材料，以及在所述第二绝缘材料上形成第二导电材料，其中所述第二导电材料形成在所述开口中并接触所述衬底的非掺杂区域。

53. 发明授权

US07056795B2 Thin-film transistor used as heating element for microreaction chamber 有权
公开(公告)号：US07056795B2
公开(公告)日：2006-06-06
申请号：US11028985
申请日：2005-01-03
申请人： Frank R. Bryant
发明人： Frank R. Bryant
IPC分类号： H01L21/336
CPC分类号： H01L29/78696 , B01J19/0093 , B01J2219/00783 , B01J2219/00828 , B01J2219/00853 , B01J2219/00873 , B01L3/5027 , B41J2/14129 , F24V99/00 , G01N25/4826 , G01N2035/00376 , H01L29/66765 , H01L29/78624 , H05B3/26 , H05B2203/013 , H05B2203/017
摘要： The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.

54. 发明授权

US06977185B2 Printhead integrated circuit 有权
标题翻译：打印头集成电路
公开(公告)号：US06977185B2
公开(公告)日：2005-12-20
申请号：US10214081
申请日：2002-08-06
申请人： Frank R. Bryant , Joseph M. Torgerson , Angela White Bakkom
发明人： Frank R. Bryant , Joseph M. Torgerson , Angela White Bakkom
IPC分类号： B41J2/05 , B41J2/14 , B41J2/16 , B41J2/175 , H01L21/00
CPC分类号： B41J2/17556 , B41J2/14016 , B41J2/1601 , B41J2/1628 , B41J2/1629 , B41J2/1631 , B41J2/1646 , B41J2202/13
摘要： An integrated circuit is formed on a substrate. The integrated circuit includes a transistor formed in the substrate. The transistor has a gate that forms at least one closed-loop. The integrated circuit also includes an ejection element that is coupled to the transistor wherein the ejection element is disposed over the substrate without an intervening field oxide layer.
摘要翻译：在基板上形成集成电路。集成电路包括形成在衬底中的晶体管。晶体管具有形成至少一个闭环的栅极。集成电路还包括耦合到晶体管的喷射元件，其中喷射元件设置在衬底上，而没有中间场氧化物层。

55. 发明授权

US06504226B1 Thin-film transistor used as heating element for microreaction chamber 有权
标题翻译：薄膜晶体管用作微反应室的加热元件
公开(公告)号：US06504226B1
公开(公告)日：2003-01-07
申请号：US10028849
申请日：2001-12-20
申请人： Frank R. Bryant
发明人： Frank R. Bryant
IPC分类号： H01L2900
CPC分类号： H01L29/78696 , B01J19/0093 , B01J2219/00783 , B01J2219/00828 , B01J2219/00853 , B01J2219/00873 , B01L3/5027 , B41J2/14129 , F24V99/00 , G01N25/4826 , G01N2035/00376 , H01L29/66765 , H01L29/78624 , H05B3/26 , H05B2203/013 , H05B2203/017
摘要： The thin film transistor formed of polycrystalline silicon is positioned adjacent a heat reaction chamber. The gate electrode for the transistor is formed within a silicon substrate and a gate dielectric is positioned over the gate electrode. A pass transistor is coupled to the gate electrode, the pass transistor having a source/drain region in the same semiconductor substrate and positioned adjacent to the gate electrode of the thin film heating transistor. When the pass transistor is enabled, a voltage is applied to the gate electrode which causes the current to flow from the drain to the source of the thin film transistor. The current flow passes through a highly resistive region which generates heat that is transmitted to the heat reaction chamber.
摘要翻译：由多晶硅形成的薄膜晶体管位于热反应室附近。用于晶体管的栅电极形成在硅衬底内，并且栅极电介质位于栅极上。传输晶体管耦合到栅电极，传输晶体管在同一半导体衬底中具有源极/漏极区域并且邻近薄膜加热晶体管的栅电极定位。当传输晶体管被使能时，电压被施加到栅电极，这导致电流从漏极流到薄膜晶体管的源极。电流流经高电阻区，产生传递到热反应室的热量。

56. 发明授权

US6132032A Thin-film print head for thermal ink-jet printers 有权
标题翻译：用于热喷墨打印机的薄膜打印头
公开(公告)号：US6132032A
公开(公告)日：2000-10-17
申请号：US373827
申请日：1999-08-13
申请人： Frank R. Bryant , John E. Turner
发明人： Frank R. Bryant , John E. Turner
IPC分类号： B41J2/14 , B41J2/05
CPC分类号： B41J2/14072 , B41J2/14129 , B41J2202/13
摘要： A thin-film print head is provided that includes at least one MOSTFT transistor, at least one resistor, a conductive line between the transistor and resistor. External interconnects between the internal circuitry of print head and external driver circuitry are provided. The thin-film print head device is adjacent to an ink barrier and an orifice plate that together define the firing chamber. Each firing chamber has associated with it a respective thin-film resistor of the print head that is selectively driven by a respective transistor. The transistor includes a source, a gate, a channel, and a drain, wherein the source, channel, and drain are formed by a first polysilicon layer. The MOSTFT transistor selectively drives the resistor with sufficient current to vaporize ink in the chamber and eject ink therefrom. The MOSTFT transistor allows the print head to be manufactured on a relatively inexpensive, non-silicon substrate or a less expensive silicon substrate, due to the less restrictive criteria for the substrate material required by MOSTFT transistors. The substrate may also comprise a material that provides enhanced thermal conductivity to act as a substantial heat sink for the print head.
摘要翻译：提供薄膜打印头，其包括至少一个MOSTFT晶体管，至少一个电阻器，晶体管和电阻器之间的导线。提供打印头内部电路与外部驱动电路之间的外部互连。薄膜打印头装置与油墨阻挡件和一起限定燃烧室的孔板相邻。每个发射室与其相关联的是打印头的相应薄膜电阻器，其由相应的晶体管选择性地驱动。晶体管包括源极，栅极，沟道和漏极，其中源极，沟道和漏极由第一多晶硅层形成。 MOSTFT晶体管选择性地驱动具有足够电流的电阻器以使腔室中的墨水蒸发并从中喷出墨水。由于MOSTFT晶体管所需的衬底材料限制较少的标准，MOSTFT晶体管允许在相对便宜的非硅衬底或较便宜的硅衬底上制造打印头。衬底还可以包括提供增强的导热性以用作打印头的实质散热器的材料。

57. 发明授权

US06093963A Dual landing pad structure including dielectric pocket 失效
标题翻译：双重着陆垫结构包括电介质袋
公开(公告)号：US06093963A
公开(公告)日：2000-07-25
申请号：US943382
申请日：1997-10-02
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/528 , H01L27/11 , H01L23/48
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L27/11 , H01L2224/05558 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/3011
摘要： A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：形成具有电介质袋的双重着陆垫结构。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

58. 发明授权

US6046483A Planar isolation structure in an integrated circuit 失效
标题翻译：集成电路中的平面隔离结构
公开(公告)号：US6046483A
公开(公告)日：2000-04-04
申请号：US964738
申请日：1997-11-05
申请人： Mark R. Tesauro , Frank R. Bryant
发明人： Mark R. Tesauro , Frank R. Bryant
IPC分类号： H01L21/76 , H01L21/762 , H01L27/02
CPC分类号： H01L21/76216 , H01L21/7621
摘要： A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces. The substrate in the openings is then oxidized to form a field oxide region substantially coplanar with the original substrate surface.
摘要翻译：提供了一种用于在主体的半导体表面形成隔离结构的方法，以及由此形成的隔离结构。在衬底表面的选定区域上形成掩模层; 掩模层优选地包括覆盖衬垫氧化物层的氮化物层。对掩模层进行图案化和蚀刻以形成露出衬底表面的选定区域的开口。凹口在开口中形成在基底中。优选地，衬垫氧化物层的一部分在形成底切区域的氮化物层下被各向同性地蚀刻。在沿着侧壁填充在底切中的凹部中的衬底上形成蚀刻停止层。在蚀刻停止层上方形成优选氮化物的第二掩蔽层，并进行各向异性蚀刻以在开口中形成氮化物侧壁。蚀刻停止层可以从水平表面被蚀刻掉。然后将开口中的衬底氧化以形成与原始衬底表面基本上共面的场氧化物区域。

59. 发明授权

US5914518A Method of forming a metal contact to landing pad structure in an integrated circuit 失效
公开(公告)号：US5914518A
公开(公告)日：1999-06-22
申请号：US759759
申请日：1996-12-03
申请人： Loi N. Nguyen , Frank R. Bryant
发明人： Loi N. Nguyen , Frank R. Bryant
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/00
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. Additionally, the landing pad will enhance planarization to provide for better step coverage of the metal contact in the second opening.

60. 发明授权

US5543343A Method fabricating an integrated circuit 失效
标题翻译：制造集成电路的方法
公开(公告)号：US5543343A
公开(公告)日：1996-08-06
申请号：US172636
申请日：1993-12-22
申请人： Frank R. Bryant , Robert L. Hodges
发明人： Frank R. Bryant , Robert L. Hodges
IPC分类号： H01L21/76 , H01L21/28 , H01L21/314 , H01L21/32 , H01L21/762 , H01L21/768 , H01L23/522 , H01L29/51 , H01L29/78 , H01L21/70 , H01L27/00
CPC分类号： H01L21/28176 , H01L21/28202 , H01L21/3145 , H01L21/32 , H01L21/76216 , H01L29/513 , H01L29/518
摘要： A method is provided for forming a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A gate oxide layer is formed over a silicon substrate. A first polysilicon layer is formed over the gate oxide layer and a nitride layer is formed over the first polysilicon layer. The first polysilicon and nitride layers are then patterned and etched to form an opening which exposes a portion of the gate oxide layer. An oxidation step is then performed to form a field oxide region in the opening. The field oxide region is formed to a thickness having an upper surface substantially planar with an upper surface of the first polysilicon layer. The nitride layer is then removed and the gate oxide and first polysilicon layers are patterned and etched to form a gate electrode and an interconnect. A silicide or other conductive layer, such as a second polysilicon layer, may be formed over the remaining first polysilicon regions and a portion of the field oxide layer to connect the gate and interconnect since the upper surface of the first polysilicon layer is substantially planar with the upper surface of the field oxide region and does not cross over the field oxide region.
摘要翻译：提供一种用于形成半导体集成电路的平面的方法和根据该集成电路形成的集成电路。在硅衬底上形成栅氧化层。在栅极氧化物层上形成第一多晶硅层，在第一多晶硅层上形成氮化物层。然后对第一多晶硅和氮化物层进行构图和蚀刻，以形成露出栅极氧化物层的一部分的开口。然后进行氧化步骤以在开口中形成场氧化物区域。场氧化物区域形成为具有与第一多晶硅层的上表面大致平坦的上表面的厚度。然后去除氮化物层，并对栅极氧化物和第一多晶硅层进行图案化和蚀刻以形成栅电极和互连。可以在剩余的第一多晶硅区域和场氧化物层的一部分上形成硅化物或其它导电层，例如第二多晶硅层，以连接栅极和互连，因为第一多晶硅层的上表面基本上是平面的，场氧化物区域的上表面并且不与场氧化物区域交叉。

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