专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5705427A Method of forming a landing pad structure in an integrated circuit 失效
公开(公告)号：US5705427A
公开(公告)日：1998-01-06
申请号：US420105
申请日：1995-04-11
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/528 , H01L27/11 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L27/11 , H01L2224/05558 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/3011
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

2. 发明授权

US06093963A Dual landing pad structure including dielectric pocket 失效
标题翻译：双重着陆垫结构包括电介质袋
公开(公告)号：US06093963A
公开(公告)日：2000-07-25
申请号：US943382
申请日：1997-10-02
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/528 , H01L27/11 , H01L23/48
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L27/11 , H01L2224/05558 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/3011
摘要： A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：形成具有电介质袋的双重着陆垫结构。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

3. 发明授权

US5909636A Method of forming a landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：US5909636A
公开(公告)日：1999-06-01
申请号：US802811
申请日：1997-02-18
申请人： Loi N. Nguyen , Frank R. Bryant , Artur P. Balasinski
发明人： Loi N. Nguyen , Frank R. Bryant , Artur P. Balasinski
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L21/44
CPC分类号： H01L21/28525 , H01L2924/14
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一开口中以及与第一开口相邻的第一电介质层的一部分上形成双重多晶硅着陆焊盘。双层焊盘优选由两个多晶硅着陆焊盘形成，其中氧化物形成在两个多晶硅层的一部分之间并在第一多晶硅层上方。该着陆垫将在制造的这个阶段增强晶片的平面化，并且容许随后形成的金属触点的未对准而不会侵入设计规则。

4. 发明授权

US5945738A Dual landing pad structure in an integrated circuit 失效
标题翻译：集成电路中的双层焊盘结构
公开(公告)号：US5945738A
公开(公告)日：1999-08-31
申请号：US760098
申请日：1996-12-03
申请人： Loi N. Nguyen , Frank R. Bryant , Artur P. Balasinski
发明人： Loi N. Nguyen , Frank R. Bryant , Artur P. Balasinski
IPC分类号： H01L21/285 , H01L21/768 , H01L23/485 , H01L23/522 , H01L23/528 , H01L27/02
CPC分类号： H01L24/05 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L2224/0401 , H01L2224/05599 , H01L2224/05624 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A dual polysilicon landing pad is formed in the first opening and on a portion of the first dielectric layer adjacent the first opening. The dual landing pad is preferably formed from two polysilicon landing pads with an oxide formed in between a portion of the two polysilicon layers and over the first polysilicon layer. This landing pad will enhance the planarization of the wafer at this stage of the manufacturing and tolerate misalignment of subsequently formed metal contacts without invading design rules.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一开口中以及与第一开口相邻的第一电介质层的一部分上形成双重多晶硅着陆焊盘。双层焊盘优选由两个多晶硅着陆焊盘形成，其中氧化物形成在两个多晶硅层的一部分之间并在第一多晶硅层上方。该着陆垫将在制造的这个阶段增强晶片的平面化，并且容许随后形成的金属触点的未对准而不会侵入设计规则。

5. 发明授权

US5894160A Method of forming a landing pad structure in an integrated circuit 失效
公开(公告)号：US5894160A
公开(公告)日：1999-04-13
申请号：US725621
申请日：1996-10-03
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

6. 发明授权

US5702979A Method of forming a landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：US5702979A
公开(公告)日：1997-12-30
申请号：US361760
申请日：1994-12-22
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductrive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电触头开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

7. 再颁专利

USRE36938E Method of forming a landing pad structure in an integrated circuit 有权
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：USRE36938E
公开(公告)日：2000-10-31
申请号：US134727
申请日：1998-08-17
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

8. 发明授权

US5956615A Method of forming a metal contact to landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成与接地焊盘结构的金属接触的方法
公开(公告)号：US5956615A
公开(公告)日：1999-09-21
申请号：US362655
申请日：1994-12-22
申请人： Loi N. Nguyen , Frank R. Bryant
发明人： Loi N. Nguyen , Frank R. Bryant
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A landing pad is formed over the first dielectric layer and in the opening. The landing pad preferably comprises a doped polysilicon layer disposed in the first opening and over a portion of the first dielectric layer. The landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A second dielectric layer having an opening therethrough is formed over the landing pad having an opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. Additionally, the landing pad will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成着陆垫。着陆垫优选地包括设置在第一开口中并在第一介电层的一部分上方的掺杂多晶硅层。着陆垫将提供较小的几何形状，并符合严格的设计规则，例如接触空间到门。具有穿过其中的开口的第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的开口。在接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。另外，着陆垫将增强平面化以提供第二开口中的金属接触件的更好的台阶覆盖。

9. 发明授权

US5423939A Method for forming contact plugs in integrated circuits 失效
标题翻译：在集成电路中形成接触塞的方法
公开(公告)号：US5423939A
公开(公告)日：1995-06-13
申请号：US110486
申请日：1993-08-23
申请人： Frank R. Bryant , Loi N. Nguyen
发明人： Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/768 , B44C1/22
CPC分类号： H01L21/76877 , H01L21/7684
摘要： According to the present invention, a method is provided for forming contact vias in an integrated circuit. Initially, a first protective layer is formed on an insulating layer, and an opening is created through the insulating layer where a contact is to be made. A conductive layer is deposited over the protective layer and partially fills the opening, forming a conductive plug in the opening. A second protective layer is then formed over the conductive plug. Portions of the conductive layer which were formed over the first protective layer are removed. During removal of those portions of the conductive layer, the second protective layer protects the conductive plug from damage. The first and second protective layers are then removed, leaving the conductive plug in the opening in the insulating layer. A conductive contact can now be made by depositing a second conductive layer over the conductive plug.
摘要翻译：根据本发明，提供了一种在集成电路中形成接触孔的方法。首先，在绝缘层上形成第一保护层，并且通过要进行接触的绝缘层形成开口。导电层沉积在保护层上并部分地填充开口，在开口中形成导电塞。然后在导电插塞上形成第二保护层。在第一保护层上形成的导电层的部分被去除。在去除导电层的那些部分期间，第二保护层保护导电插头免受损坏。然后去除第一和第二保护层，将导电塞留在绝缘层中的开口中。现在可以通过在导电插塞上沉积第二导电层来进行导电接触。

10. 发明授权

US5489797A Local interconnect structure 失效
标题翻译：本地互连结构
公开(公告)号：US5489797A
公开(公告)日：1996-02-06
申请号：US420353
申请日：1995-04-11
申请人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
发明人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
IPC分类号： H01L21/768 , H01L23/532 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L27/1104 , H01L21/76895 , H01L23/53271 , H01L2924/0002 , Y10S257/903
摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
摘要翻译：互连结构及其形成方法适用于诸如SRAM器件的集成电路。该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式