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1. 发明授权

US06093963A Dual landing pad structure including dielectric pocket 失效
标题翻译：双重着陆垫结构包括电介质袋
公开(公告)号：US06093963A
公开(公告)日：2000-07-25
申请号：US943382
申请日：1997-10-02
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/528 , H01L27/11 , H01L23/48
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L27/11 , H01L2224/05558 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/3011
摘要： A dual landing pad structure is formed with a dielectric pocket. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：形成具有电介质袋的双重着陆垫结构。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

2. 发明授权

US5705427A Method of forming a landing pad structure in an integrated circuit 失效
公开(公告)号：US5705427A
公开(公告)日：1998-01-06
申请号：US420105
申请日：1995-04-11
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen , Artur P. Balasinski
IPC分类号： H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L23/485 , H01L23/528 , H01L27/11 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L27/11 , H01L2224/05558 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/04941 , H01L2924/14 , H01L2924/3011
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

3. 发明授权

US5894160A Method of forming a landing pad structure in an integrated circuit 失效
公开(公告)号：US5894160A
公开(公告)日：1999-04-13
申请号：US725621
申请日：1996-10-03
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

4. 发明授权

US5702979A Method of forming a landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：US5702979A
公开(公告)日：1997-12-30
申请号：US361760
申请日：1994-12-22
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductrive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电触头开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

5. 再颁专利

USRE36938E Method of forming a landing pad structure in an integrated circuit 有权
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：USRE36938E
公开(公告)日：2000-10-31
申请号：US134727
申请日：1998-08-17
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电接触开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

6. 发明授权

US5489797A Local interconnect structure 失效
标题翻译：本地互连结构
公开(公告)号：US5489797A
公开(公告)日：1996-02-06
申请号：US420353
申请日：1995-04-11
申请人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
发明人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
IPC分类号： H01L21/768 , H01L23/532 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L27/1104 , H01L21/76895 , H01L23/53271 , H01L2924/0002 , Y10S257/903
摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
摘要翻译：互连结构及其形成方法适用于诸如SRAM器件的集成电路。该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

7. 发明授权

US5196909A Capacitor for DRAM cell 失效
标题翻译： DRAM单元电容器
公开(公告)号：US5196909A
公开(公告)日：1993-03-23
申请号：US697227
申请日：1991-05-07
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10817 , H01L28/40
摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.
摘要翻译：适用于DRAM存储单元的电容器由多层多晶硅组成。存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

8. 发明授权

US5336916A SRAM cell and structure with polycrystalline p-channel load devices 失效
标题翻译：具有多晶p沟道负载器件的SRAM单元和结构
公开(公告)号：US5336916A
公开(公告)日：1994-08-09
申请号：US919958
申请日：1992-07-27
申请人： Tsiu C. Chan , Frank R. Bryant , Lisa K. Jorgenson
发明人： Tsiu C. Chan , Frank R. Bryant , Lisa K. Jorgenson
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/78
CPC分类号： H01L27/11 , H01L27/1108 , Y10S257/903
摘要： An integrated circuit structure is suitable for use with SRAM memory devices. P-channel load devices are used in a 6-transistor SRAM cell. The P-channel devices are formed as polycrystalline silicon field effect transistors above the N-channel field effect transistors, which are formed in the substrate. In order to avoid formation of a P-N junction, a barrier layer is formed between P-type and N-type source/drain regions. The preferred barrier is a bilayer formed from a conductive material such as silicide over a doped polycrystalline silicon layer.
摘要翻译：集成电路结构适用于SRAM存储器件。 P沟道负载器件用于6晶体管SRAM单元。 P沟道器件形成在形成在衬底中的N沟道场效应晶体管之上的多晶硅场效应晶体管。为了避免形成P-N结，在P型和N型源极/漏极区之间形成阻挡层。优选的屏障是由掺杂多晶硅层上的诸如硅化物的导电材料形成的双层。

9. 发明授权

US5300797A Coplanar twin-well integrated circuit structure 失效
标题翻译：共面双阱集成电路结构
公开(公告)号：US5300797A
公开(公告)日：1994-04-05
申请号：US860980
申请日：1992-03-31
申请人： Frank R. Bryant , Tsiu C. Chan , Kuei-Wu Huang
发明人： Frank R. Bryant , Tsiu C. Chan , Kuei-Wu Huang
IPC分类号： H01L27/08 , H01L21/8238 , H01L23/544 , H01L27/02
CPC分类号： H01L21/823892 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002
摘要： A structure and method is provided for fabricating an integrated circuit having an N-type well and a P-type well, with the upper surfaces of the N-type well and the P-type well coplanar. An insulating layer is formed over the integrated circuit. A first masking layer is formed over the insulating layer to define locations of a first well to be formed. An impurity of a first conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a first region. The first masking layer is removed, and a second masking layer is formed over the insulating layer to define locations of a second well to be formed. An impurity of a second conductivity type is implanted into the semiconductor substrate of the integrated circuit to form a second region. The second masking layer is then removed. The integrated circuit is thermally heated to form the first and second wells in the substrate. If desired, sets of alignment keys may be formed in a semiconductor wafer by first forming a layer of insulating material over a semiconductor wafer, followed by forming a layer of masking material to define the locations of the sets of alignment keys and anisotropically etching into the semiconductor wafer to form the sets of alignment keys.
摘要翻译：提供一种用于制造具有N型阱和P型阱的集成电路的结构和方法，其中N型阱的上表面和P型阱共面。在集成电路上形成绝缘层。在绝缘层上形成第一掩模层以限定要形成的第一阱的位置。将第一导电类型的杂质注入到集成电路的半导体衬底中以形成第一区域。去除第一掩模层，并且在绝缘层上形成第二掩模层以限定要形成的第二阱的位置。将第二导电类型的杂质注入到集成电路的半导体衬底中以形成第二区域。然后去除第二掩蔽层。集成电路被热加热以在衬底中形成第一和第二阱。如果需要，可以在半导体晶片中形成一组对准键，首先在半导体晶片上形成绝缘材料层，然后形成掩模材料层，以限定对齐键组和各向异性蚀刻的位置半导体晶片形成一组对准键。

10. 发明授权

US5500557A Structure and method for fabricating integrated circuits 失效
标题翻译：集成电路制造的结构和方法
公开(公告)号：US5500557A
公开(公告)日：1996-03-19
申请号：US126673
申请日：1993-09-24
申请人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
发明人： Tsiu C. Chan , Frank R. Bryant , Lun-Tseng Lu , Che-Chia Wei
IPC分类号： H01L23/528 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5283 , H01L23/53271 , H01L2924/0002
摘要： A structure and method for fabricating integrated circuits which provides for the detection of residual conductive material. A first conductive layer is deposited over the integrated circuit and patterned to define a first interconnect layer. An insulating layer is then formed over the integrated circuit. A second conductive layer is then deposited and patterned to define a second interconnect layer. Residual conductive material can be formed during patterning of the second interconnect layer when portions of the second conductive layer remain adjacent to the vertical sidewalls of the first interconnect layer. To make the residual conductive material easier to detect, the conductivity of the residual conductive material is increased by either implanting impurities into the integrated circuit or siliciding the residual conductive material with a refractory metal.
摘要翻译：用于制造集成电路的结构和方法，其提供残留导电材料的检测。第一导电层沉积在集成电路上并被图案化以限定第一互连层。然后在集成电路上形成绝缘层。然后沉积和图案化第二导电层以限定第二互连层。当第二导电层的部分保持与第一互连层的垂直侧壁相邻时，可以在图案化第二互连层期间形成剩余的导电材料。为了使残留的导电材料更易于检测，通过将杂质注入集成电路或用难熔金属硅化残留的导电材料来增加剩余导电材料的导电性。

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