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1. 发明授权

US6046483A Planar isolation structure in an integrated circuit 失效
标题翻译：集成电路中的平面隔离结构
公开(公告)号：US6046483A
公开(公告)日：2000-04-04
申请号：US964738
申请日：1997-11-05
申请人： Mark R. Tesauro , Frank R. Bryant
发明人： Mark R. Tesauro , Frank R. Bryant
IPC分类号： H01L21/76 , H01L21/762 , H01L27/02
CPC分类号： H01L21/76216 , H01L21/7621
摘要： A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces. The substrate in the openings is then oxidized to form a field oxide region substantially coplanar with the original substrate surface.
摘要翻译：提供了一种用于在主体的半导体表面形成隔离结构的方法，以及由此形成的隔离结构。在衬底表面的选定区域上形成掩模层; 掩模层优选地包括覆盖衬垫氧化物层的氮化物层。对掩模层进行图案化和蚀刻以形成露出衬底表面的选定区域的开口。凹口在开口中形成在基底中。优选地，衬垫氧化物层的一部分在形成底切区域的氮化物层下被各向同性地蚀刻。在沿着侧壁填充在底切中的凹部中的衬底上形成蚀刻停止层。在蚀刻停止层上方形成优选氮化物的第二掩蔽层，并进行各向异性蚀刻以在开口中形成氮化物侧壁。蚀刻停止层可以从水平表面被蚀刻掉。然后将开口中的衬底氧化以形成与原始衬底表面基本上共面的场氧化物区域。

2. 发明授权

US5834360A Method of forming an improved planar isolation structure in an integrated circuit 失效
标题翻译：在集成电路中形成改进的平面隔离结构的方法
公开(公告)号：US5834360A
公开(公告)日：1998-11-10
申请号：US690738
申请日：1996-07-31
申请人： Mark R. Tesauro , Frank R. Bryant
发明人： Mark R. Tesauro , Frank R. Bryant
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76216 , H01L21/7621
摘要： A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces. The substrate in the openings is then oxidized to form a field oxide region substantially coplanar with the original substrate surface.
摘要翻译：提供了一种用于在主体的半导体表面形成隔离结构的方法，以及由此形成的隔离结构。在衬底表面的选定区域上形成掩模层; 掩模层优选地包括覆盖衬垫氧化物层的氮化物层。对掩模层进行图案化和蚀刻以形成露出衬底表面的选定区域的开口。凹口在开口中形成在基底中。优选地，衬垫氧化物层的一部分在形成底切区域的氮化物层下被各向同性地蚀刻。在沿着侧壁填充在底切中的凹部中的衬底上形成蚀刻停止层。在蚀刻停止层上方形成优选氮化物的第二掩蔽层，并进行各向异性蚀刻以在开口中形成氮化物侧壁。蚀刻停止层可以从水平表面被蚀刻掉。然后将开口中的衬底氧化以形成与原始衬底表面基本上共面的场氧化物区域。

3. 发明授权

US06752900B2 Vacuum loadlock ultraviolet bake for plasma etch 有权
标题翻译：真空负压锁紫外线烘烤用于等离子体蚀刻
公开(公告)号：US06752900B2
公开(公告)日：2004-06-22
申请号：US09969197
申请日：2001-10-02
申请人： Mark R. Tesauro
发明人： Mark R. Tesauro
IPC分类号： H05H100
CPC分类号： H01L21/67115 , G03F7/40 , H01L21/67069
摘要： An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next semiconductor wafer to be plasma etched, an exit vacuum loadlock for transporting the semiconductor wafers out of the reaction chamber after the plasma etching process, and a source of ultraviolet light. Exposing the semiconductor wafer to the ultraviolet light cures the photo-resist patterns, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation. Curing the photo-resist patterns while the semiconductor wafer is being held during the process cycle in the entrance vacuum loadlock, increases efficiency and productivity.
摘要翻译：一种用于等离子体蚀刻具有光刻胶图案的半导体晶片的改进的真空等离子体蚀刻装置。改进的等离子体蚀刻装置具有反应室，其中在处理循环期间执行等离子体蚀刻，用于保持待等离子体蚀刻的下一半导体晶片的入口真空负载锁，用于将半导体晶片输送出反应室的出口真空负载锁在等离子体蚀刻工艺之后，以及紫外线源。将半导体晶片暴露于紫外线固化光刻胶图案，从而改善CD色散，增强图案转印和防止光致抗蚀剂网状结构。在入口真空负载锁定期间，在半导体晶片被保持的过程中固化光刻胶图案，提高了效率和生产率。

4. 发明授权

US6077387A Plasma emission detection for process control via fluorescent relay 有权
标题翻译：通过荧光继电器进行过程控制的等离子体发射检测
公开(公告)号：US6077387A
公开(公告)日：2000-06-20
申请号：US248359
申请日：1999-02-10
申请人： Mark R. Tesauro
发明人： Mark R. Tesauro
IPC分类号： H01J37/32 , H01L21/00
CPC分类号： H01L21/67069 , H01J37/32935 , H01J37/3299
摘要： Method and system for monitoring a plasma etch process performed in a plasma processing chamber, the method and system being capable of accurately monitoring and controlling the plasma etch process without being affected by the change in a plasma light emission transmission characteristically caused by process polymer depositions on a detecting surface or sampling window. The system includes a plasma processing chamber having a wafer to be processed arranged therein, having at least one window to allow fluorescent light emissions to pass through, a plasma generation means for generating a plasma in the processing chamber, a fluorescent target located within the plasma processing chamber for producing a fluorescent light emission, an optical sensor external to the chamber for sensing the fluorescent light emission through the window, a detector for converting the sensed fluorescent light emissions into a signal recognizable by a controller and a controller for controlling the state of the plasma process being performed on the wafer.
摘要翻译：用于监测在等离子体处理室中执行的等离子体蚀刻工艺的方法和系统，所述方法和系统能够精确地监测和控制等离子体蚀刻工艺，而不受由过程聚合物沉积特征性地引起的等离子体发光透射的变化的影响检测面或采样窗。该系统包括具有待处理晶片的等离子体处理室，具有至少一个允许荧光发射通过的窗口，用于在处理室中产生等离子体的等离子体产生装置，位于等离子体内的荧光目标用于产生荧光发射的处理室，用于感测通过窗口的荧光发射的室外的光学传感器，用于将感测到的荧光发射转换成由控制器可识别的信号的检测器，以及用于控制在晶片上执行等离子体处理。

5. 发明授权

US06339028B2 Vacuum loadlock ultra violet bake for plasma etch 有权
标题翻译：用于等离子体蚀刻的真空负压锁紫外线烘烤
公开(公告)号：US06339028B2
公开(公告)日：2002-01-15
申请号：US09300095
申请日：1999-04-27
申请人： Mark R. Tesauro
发明人： Mark R. Tesauro
IPC分类号： H01L2100
CPC分类号： H01L21/67115 , G03F7/40 , H01L21/67069
摘要： An improved vacuum plasma etching device for plasma etching semiconductor wafers that have a photo-resist pattern. The improved plasma etching device has a reaction chamber in which the plasma etching is performed during a process cycle, an entrance vacuum loadlock for holding the next semiconductor wafer to be plasma etched, an exit vacuum loadlock for transporting the semiconductor wafers out of the reaction chamber after the plasma etching process, and a source of ultraviolet light. Exposing the semiconductor wafer to the ultraviolet light cures the photo-resist patterns, thereby improving CD dispersion, enhancing pattern transfer, and preventing photo-resist reticulation. Curing the photo-resist patterns while the semiconductor wafer is being held during the process cycle in the entrance vacuum loadlock, increases efficiency and productivity.
摘要翻译：一种用于等离子体蚀刻具有光刻胶图案的半导体晶片的改进的真空等离子体蚀刻装置。改进的等离子体蚀刻装置具有反应室，其中在处理循环期间执行等离子体蚀刻，用于保持待等离子体蚀刻的下一半导体晶片的入口真空负载锁，用于将半导体晶片输送出反应室的出口真空负载锁在等离子体蚀刻工艺之后，以及紫外线源。将半导体晶片暴露于紫外线固化光刻胶图案，从而改善CD色散，增强图案转印和防止光致抗蚀剂网状结构。在入口真空负载锁定期间，在半导体晶片被保持的过程中固化光刻胶图案，提高了效率和生产率。

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