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    • 51. 发明授权
    • Phase modulator
    • 相位调制器
    • US06891445B2
    • 2005-05-10
    • US10458279
    • 2003-06-11
    • Noboru KusamaKatsuya KitadaMasahiro AkiyamaTakashi NakagawaNoriko Sato
    • Noboru KusamaKatsuya KitadaMasahiro AkiyamaTakashi NakagawaNoriko Sato
    • H04L27/20H03C3/00
    • H04L27/2071
    • In response to changes in an input binary digital signal, a 3rd order cosine pulse waveform, which, when it is changed in the increasing direction, has “0” level in a first period of T/12 (T corresponding to one-half cycle of the binary digital signal), is changed as a waveform of (h/2)(1+cos(3πt/T)+π/4) in the next period of 4T/12 (−5T/12≦t≦−T/12) and has an h (constant) level in the remaining period of T/12, and when it is changed in the reducing direction, has the h level in the first period of T/12, is changed as a waveform of (h/2)(1+cos(3πt/T)−π/4) in the next period of 4T/12 (T/12≦t≦5T/12) and also has “0” level in the remaining period of T/12. By using this pulse wave, a flat part is generated in a time width of T/12 with respect to a judgment point. It is thus possible to improve the immunity to the effects of digital signal jitter, obtain change judgment with a sole single pulse and reduce the circuit scale and the power consumption.
    • 响应于输入二进制数字信号的变化,三阶余弦脉冲波形当其在增加方向上改变时在T / 12的第一周期(对应于半周期的T)中具有“0”电平 在二进制数字信号的下一个周期中,作为(h / 2)(1 + cos(3pit / T)+ pi / 4)的波形而变化(-5T / 12 <= t < -T / 12),并且在T / 12的剩余时间段中具有h(常数)电平,并且当在减小方向上改变时,在T / 12的第一周期中具有h电平作为波形 在4T / 12的下一个周期(T / 12 <= t <= 5T / 12)中的(h / 2)(1 + cos(3pit / T)-pi / 4) 剩余时间T / 12。 通过使用该脉波,相对于判断点,以T / 12的时间宽度产生平坦部。 因此,可以提高对数字信号抖动的影响的抗扰性,用唯一的单脉冲获得变化判断,并减小电路规模和功耗。
    • 52. 发明授权
    • Modulator and oscillator for microwave and milliwave use
    • 用于微波和微波的调制器和振荡器
    • US06720833B2
    • 2004-04-13
    • US10020187
    • 2001-12-18
    • Bun KobayashiMasahiro Akiyama
    • Bun KobayashiMasahiro Akiyama
    • H03B518
    • H03D9/0641H03B5/1888H03C1/12H03C3/20
    • The present invention provides a modulator which has a high degree of modulation and a good modulation sensitivity. The modulator comprises an oscillating circuit and a resonator portion, and this resonator portion comprises a reflective circuit board, a coupling line which is disposed on the reflective circuit board, a coupled load which is coupled to one end of the coupling line, a dielectric resonator which is disposed on the reflective circuit board and which is magnetically coupled with the coupling line, a window portion which is formed in the undersurface of the reflective circuit board directly beneath the coupling line, a waveguide resonator which is disposed on the undersurface of the reflective circuit board in the area that includes the window portion, and which is magnetically coupled with the coupling line, and a varactor diode which is inserted between the opposite signal conductor surfaces and of the waveguide resonator, and to which the input modulating signal terminal is connected. The other end of the coupling line constitute the output port of the resonator portion, and is connected to the input port of the oscillating circuit, and the end portion of the coupled load that is not coupled to the abovementioned coupling line is grounded.
    • 本发明提供一种具有高调制度和良好调制灵敏度的调制器。 调制器包括振荡电路和谐振器部分,该谐振器部分包括反射电路板,耦合线设置在反射电路板上,耦合负载耦合到耦合线的一端,介质谐振器 其设置在反射电路板上并且与耦合线磁耦合,窗口部分形成在反射电路板的下表面正下方的耦合线之下,波导谐振器设置在反射器的下表面上 包括窗口部分并且与耦合线磁耦合的区域中的电路板和插入在相对的信号导体表面和波导谐振器之间的变容二极管,并且输入调制信号端子连接到该二极管 。 耦合线的另一端构成谐振器部分的输出端口,并连接到振荡电路的输入端口,并且未耦合到上述耦合线路的耦合负载的端部接地。
    • 57. 发明授权
    • Frequency-dividing circuit
    • 频率分流电路
    • US5111489A
    • 1992-05-05
    • US586446
    • 1990-09-21
    • Koutarou TanakaMakoto ShikataMasahiro Akiyama
    • Koutarou TanakaMakoto ShikataMasahiro Akiyama
    • H03K23/44H03K3/037H03K23/00
    • H03K3/037
    • In a frequency-dividing circuit for producing an output having a frequency half that of its input, a pair of terminals of a latch circuit are connected to input terminals of a pair of amplify/delay means, and are also connected to receive through a pair of transistors, the outputs of the amplify/delay means. A single-phase input signal is input to the control electrodes of the transistors to turn on and off the transistors. When the transistors are turned from off to on, the output states of the amplify/delay means are transferred through the transistors to invert the latch circuit, and the states of complementary terminals of the latch circuits are in turn transferred through the amplify/delay means to invert the output states of the outputs of the amplify/delay means. When the transistors are turned from on to off, no change occurs in the states of the circuit. In this way, the states of the circuit are inverted each time the transistors are turned from off to on. A frequency-divided output can therefore be derived at one of the outputs of the first and second amplify/delay means. Either one or both of the first and second inverters may be replaced by a NAND gate or a NOR gate for permitting reset of the circuit.