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51. 发明授权

US07749903B2 Gate patterning scheme with self aligned independent gate etch 失效
标题翻译：具有自对准独立栅极蚀刻的栅极图案化方案
公开(公告)号：US07749903B2
公开(公告)日：2010-07-06
申请号：US12027444
申请日：2008-02-07
申请人： Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
发明人： Scott D. Halle , Matthew E. Colburn , Bruce B. Doris , Thomas W. Dyer
IPC分类号： H01L21/44
CPC分类号： H01L21/32139 , H01L21/266 , H01L21/28123 , H01L21/823828
摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.
摘要翻译：公开了一种用于自对准栅极图案化的方法。使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。选择掩模材料以便于选择性蚀刻。当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

52. 发明授权

US07741721B2 Electrical fuses and resistors having sublithographic dimensions 失效
标题翻译：具有亚光刻尺寸的电气保险丝和电阻器
公开(公告)号：US07741721B2
公开(公告)日：2010-06-22
申请号：US11831236
申请日：2007-07-31
申请人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
发明人： Charles T. Black , Matthew E. Colburn , Timothy J. Dalton , Daniel C. Edelstein , Wai-Kin Li , Anthony K. Stamper , Haining S. Yang
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L21/0337 , H01L21/31144 , H01L21/32139 , H01L21/76816 , H01L23/5226 , H01L23/5228 , H01L27/101 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a first set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
摘要翻译：提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。包括导体或半导体的导电结构形成在半导体衬底上。在导电结构上形成至少一个绝缘体层。在所述至少一个绝缘体层中形成凹陷区域。将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

53. 发明授权

US07708542B2 Device for holding a template for use in imprint lithography 有权
标题翻译：用于保存用于压印光刻的模板的装置
公开(公告)号：US07708542B2
公开(公告)日：2010-05-04
申请号：US10747737
申请日：2003-12-29
申请人： Todd C. Bailey , Byung-Jin Choi , Matthew E. Colburn , Sidlgata V. Sreenivasan , Carlton G. Willson , John G. Ekerdt
发明人： Todd C. Bailey , Byung-Jin Choi , Matthew E. Colburn , Sidlgata V. Sreenivasan , Carlton G. Willson , John G. Ekerdt
IPC分类号： B29C59/02
CPC分类号： G11B5/855 , B29C35/0888 , B29C37/0053 , B29C43/003 , B29C2035/0827 , B29C2043/025 , B82Y10/00 , B82Y40/00 , G03F7/0002 , G03F9/00 , Y10S977/887
摘要： Described are imprint lithography templates, methods of forming and using the templates, and a template holder device. An imprint lithography template may include a body with a plurality of recesses on a surface of the body. The body may be of a material that is substantially transparent to activating light. At least a portion of the plurality of recesses may define features having a feature size less than about 250 nm. A template may be formed by obtaining a material that is substantially transparent to activating light and forming a plurality or recesses on a surface of the template. In some embodiments, a template may further include at least one alignment mark. In some embodiments, a template may further include a gap sensing area. An imprint lithography template may be used to form an imprinted layer in a light curable liquid disposed on a substrate. During use, the template may be disposed within a template holder. The template holder may include a body with an opening configured to receive the template, a support plate, and at least one piezo actuator coupled to the body. The piezo actuator may be configured to alter a physical dimension of the template during use.
摘要翻译：描述了压印光刻模板，形成和使用模板的方法以及模板保持装置。压印光刻模板可以包括在主体的表面上具有多个凹部的主体。身体可以是对于激活光是基本上透明的材料。多个凹部的至少一部分可以限定具有小于约250nm的特征尺寸的特征。可以通过获得对于激活光而基本上透明并在模板的表面上形成多个或多个凹陷的材料来形成模板。在一些实施例中，模板还可以包括至少一个对准标记。在一些实施例中，模板还可以包括间隙感测区域。可以使用压印光刻模板来在设置在基板上的可光固化液体中形成印刷层。在使用期间，模板可以设置在模板保持器内。模板保持器可以包括具有构造成接收模板的开口的主体，支撑板和耦合到主体的至少一个压电致动器。压电致动器可以被配置为在使用期间改变模板的物理尺寸。

54. 发明授权

US07592685B2 Device and methodology for reducing effective dielectric constant in semiconductor devices 有权
标题翻译：用于降低半导体器件中有效介电常数的器件和方法
公开(公告)号：US07592685B2
公开(公告)日：2009-09-22
申请号：US11849048
申请日：2007-08-31
申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
发明人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
IPC分类号： H01L29/93
CPC分类号： B82Y30/00 , H01L21/0332 , H01L21/31111 , H01L21/31144 , H01L21/7682 , H01L21/76829 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： Semiconductor structure includes an insulator layer having at least one interconnect feature and at least one gap formed in the insulator layer spanning more than a minimum spacing of interconnects.
摘要翻译：半导体结构包括具有至少一个互连特征的绝缘体层和形成在绝缘体层中的至少一个间隙，跨越多于互连的最小间隔。

55. 发明授权

US07544602B2 Method and structure for ultra narrow crack stop for multilevel semiconductor device 失效
标题翻译：多级半导体器件超窄裂纹停止的方法和结构
公开(公告)号：US07544602B2
公开(公告)日：2009-06-09
申请号：US11693033
申请日：2007-03-29
申请人： Lawrence A. Clevenger , Matthew E. Colburn , William F. Landers , Wai-Kin Li
发明人： Lawrence A. Clevenger , Matthew E. Colburn , William F. Landers , Wai-Kin Li
IPC分类号： H01L23/522
CPC分类号： H01L21/76808 , H01L21/7682 , H01L23/5222 , H01L23/53295 , H01L23/562 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit design and a method of fabrication and, more particularly, a semiconductor structure having an ultra narrow crack stop for use in multilevel level devices and a method of making the same. The structure includes a first dielectric layer having a first connection connecting to an underlying interconnect and a second dielectric layer having a second connection connecting to the first connection. A stop gap structure extends through the first dielectric layer and the second dielectric layer, and has a width of about less than 1 um.
摘要翻译：一种集成电路设计和制造方法，更具体地说，具有用于多电平电平装置的超窄裂缝停止的半导体结构及其制造方法。该结构包括具有连接到底层互连的第一连接的第一介电层和具有连接到第一连接的第二连接的第二介电层。止挡间隙结构延伸穿过第一介电层和第二介电层，并且具有大约小于1μm的宽度。

56. 发明申请

US20090081563A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20090081563A1
公开(公告)日：2009-03-26
申请号：US12126741
申请日：2008-05-23
申请人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
发明人： Helen Wang , Scott D. Halle , Henning Haffner , Haoren Zhuang , Klaus Herold , Matthew E. Colburn , Allen H. Gabor , Zachary Baum , Scott M. Mansfield , Jason E. Meiring
IPC分类号： G03F1/14 , G03F7/26
CPC分类号： H01L21/32139 , G03F1/36 , G03F1/70 , H01L21/0274 , H01L21/28123 , H01L21/823437 , Y10S438/942
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括在半导体衬底上沉积栅极材料，并且在栅极材料上沉积第一抗蚀剂层。使用第一掩模来图案化第一抗蚀剂层以形成第一和第二抗蚀剂特征。第一抗蚀剂特征包括半导体器件的栅极线的图案，第二抗蚀剂特征包括印刷辅助特征。使用第二掩模形成抗蚀剂模板; 第二掩模移除第二抗蚀剂特征。

57. 发明申请

US20090068837A1 LINE ENDS FORMING 有权
标题翻译：线端形成
公开(公告)号：US20090068837A1
公开(公告)日：2009-03-12
申请号：US11853353
申请日：2007-09-11
申请人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
发明人： Matthew E. Colburn , Allen H. Gabor , Scott D. Halle , Donald J. Samuels
IPC分类号： H01L21/44
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/11 , H01L27/115
摘要： Methods of forming line ends and a related memory cell including the line ends are disclosed. In one embodiment, the method includes forming a first device element and a second device element separated from the first device element by a space; and forming a first line extending from the first device element, the first line including a bulbous line end over the space and distanced from the first device element, and a second line extending from the second device element, the second line including a bulbous line end over the space and distanced from the second device element.
摘要翻译：公开了形成线端的方法和包括线端的相关存储单元。在一个实施例中，该方法包括通过空间形成与第一器件元件分离的第一器件元件和第二器件元件; 以及形成从所述第一装置元件延伸的第一线，所述第一线包括在所述空间上并与所述第一装置元件间隔开的球形线端，以及从所述第二装置元件延伸的第二线，所述第二线包括球根线端并且与第二设备元件分开。

58. 发明申请

US20090053890A1 SELECTIVE THIN METAL CAP PROCESS 有权
标题翻译：选择性金属金属工艺
公开(公告)号：US20090053890A1
公开(公告)日：2009-02-26
申请号：US11841114
申请日：2007-08-20
申请人： Griselda Bonilla , Shyng-Tsong Chen , Matthew E. Colburn , Ronald DellaGuardia , Chih-Chao Yang
发明人： Griselda Bonilla , Shyng-Tsong Chen , Matthew E. Colburn , Ronald DellaGuardia , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76825 , H01L21/76834
摘要： A method of creating metal caps on copper lines within an inter-line dielectric (ILD) deposits a thin (e.g., 5 nm) metal blanket film (e.g., Ta/TaN) on top the copper lines and dielectric, after the wafer has been planarized. Further a thin dielectric cap is formed over the metal blanket film. A photoresist coating is deposited over the thin dielectric cap and a lithographic exposure process is performed, but without a lithographic mask. A mask is not needed in this situation, because due to the reflectivity difference between copper and the ILD lying under the two thin layers, a mask pattern is automatically formed for etching away the Ta/TaN metal cap between copper lines. Thus, this mask pattern is self-aligned above the copper lines.
摘要翻译：在线间电介质（ILD）中的铜线上形成金属帽的方法在晶片已经被覆盖之后在铜线和电介质的顶部沉积薄（例如，5nm）金属覆盖膜（例如，Ta / TaN）平面化此外，在金属覆盖膜上形成薄的电介质盖。光致抗蚀剂涂层沉积在薄电介质盖上，并进行光刻曝光工艺，但没有光刻掩模。在这种情况下不需要掩模，因为由于铜和位于两个薄层之下的ILD之间的反射率差异，自动形成掩模图案以在铜线之间蚀刻掉Ta / TaN金属帽。因此，该掩模图案在铜线上方自对准。

59. 发明申请

US20080265382A1 Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same 有权
标题翻译：生产自对准面膜的非光刻方法，由相同的组成制成的文章
公开(公告)号：US20080265382A1
公开(公告)日：2008-10-30
申请号：US12164647
申请日：2008-06-30
申请人： Matthew E. Colburn , Stephen M. Gates , Jeffrey C. Hedrick , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
发明人： Matthew E. Colburn , Stephen M. Gates , Jeffrey C. Hedrick , Elbert Huang , Satyanarayana V. Nitta , Sampath Purushothaman , Muthumanickam Sankarapandian
IPC分类号： H01L23/58 , C08L53/00
CPC分类号： H05K3/0079 , H01L21/0331 , H01L21/76849 , H05K3/282 , H05K2203/1173 , Y10T428/24802
摘要： A method for forming a self aligned pattern on an existing pattern on a substrate comprising applying a coating of a solution containing a masking material in a carrier, the masking material having an affinity for portions of the existing pattern; and allowing at least a portion of the masking material to preferentially assemble to the portions of the existing pattern. The pattern may be comprised of a first set of regions of the substrate having a first atomic composition and a second set of regions of the substrate having a second atomic composition different from the first composition. The first set of regions may include one or more metal elements and the second set of regions may include a dielectric. The first and second regions may be treated to have different surface properties. Structures made in accordance with the method. Compositions useful for practicing the method.
摘要翻译：一种用于在衬底上的现有图案上形成自对准图案的方法，包括在载体中涂覆含有掩蔽材料的溶液的涂层，所述掩模材料对现有图案的部分具有亲和力; 并且允许掩模材料的至少一部分优先组装到现有图案的部分。该图案可以由具有第一原子组成的衬底的第一组区域和第二组衬底的区域组成，其具有不同于第一组成的第二原子组成。第一组区域可以包括一个或多个金属元件，并且第二组区域可以包括电介质。可以将第一和第二区域处理成具有不同的表面性质。按照该方法制造的结构。用于练习该方法的组合物。

60. 发明授权

US07439628B2 Method for improved process latitude by elongated via integration 失效
标题翻译：通过扩展通过集成改进工艺纬度的方法
公开(公告)号：US07439628B2
公开(公告)日：2008-10-21
申请号：US11474420
申请日：2006-06-26
申请人： Matthew E. Colburn
发明人： Matthew E. Colburn
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/7681 , H01L21/76829
摘要： Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.
摘要翻译：互连双镶嵌结构通过沉积在至少一个介电层的层上制造，掩模形成层用于提供双镶嵌结构的通孔级掩模层; 在通孔级掩模层中形成细长的通孔图案; 沉积一层线路电介质并通过线路级电介质层产生线路图案，并且通过细长通孔电平图案和线路电平图案的投影交点传送线路图案，从而产生对准的双大马士革结构。导电衬里层沉积在双镶嵌结构中，然后用导电填充金属填充双镶嵌结构以形成一组金属线。金属和衬里层被平坦化。

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