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51. 发明授权

US07235441B2 Nonvolatile semiconductor memory device with tapered sidewall gate and method of manufacturing the same 有权
标题翻译：具有锥形侧壁栅极的非易失性半导体存储器件及其制造方法
公开(公告)号：US07235441B2
公开(公告)日：2007-06-26
申请号：US10901347
申请日：2004-07-29
申请人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
发明人： Kan Yasui , Digh Hisamoto , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/4232 , H01L29/792
摘要： In a split gate type nonvolatile memory cell in which a MOS transistor for a nonvolatile memory using a charge storing film and a MOS transistor for selecting it are adjacently formed, the charge storing characteristic is improved and the resistance of the gate electrode is reduced. In order to prevent the thickness reduction at the corner portion of the charge storing film and improve the charge storing characteristic, a taper is formed on the sidewall of the select gate electrode. Also, in order to stably perform a silicide process for reducing the resistance of the self-aligned gate electrode, the sidewall of the select gate electrode is recessed. Alternatively, a discontinuity is formed between the upper portion of the self-aligned gate electrode and the upper portion of the select gate electrode.
摘要翻译：在其中使用电荷存储膜的非易失性存储器的MOS晶体管和用于选择它的MOS晶体管相邻形成的分离栅极型非易失性存储单元中，电荷存储特性得到改善，栅电极的电阻降低。为了防止电荷存储薄膜的拐角部分的厚度减小并且提高电荷存储特性，在选择栅电极的侧壁上形成锥形。此外，为了稳定地进行用于降低自对准栅电极的电阻的硅化物工艺，选择栅电极的侧壁凹陷。或者，在自对准栅电极的上部和选择栅电极的上部之间形成不连续。

52. 发明申请

US20060022260A1 Semiconductor device and manufacturing method of semiconductor device 失效
公开(公告)号：US20060022260A1
公开(公告)日：2006-02-02
申请号：US11182013
申请日：2005-07-15
申请人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
发明人： Digh Hisamoto , Kan Yasui , Shinichiro Kimura , Tetsuya Ishimaru
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0433 , H01L21/2815 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11521 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/792
摘要： Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.

53. 发明授权

US5374576A Method of fabricating stacked capacitor cell memory devices 失效
标题翻译：叠层电容器单元存储器件的制造方法
公开(公告)号：US5374576A
公开(公告)日：1994-12-20
申请号：US72482
申请日：1993-06-03
申请人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
发明人： Shinichiro Kimura , Naotaka Hashimoto , Yoshio Sakai , Tokuo Kure , Yoshifumi Kawamoto , Toru Kaga , Eiji Takeda
IPC分类号： H01L27/108 , H01L29/417 , H01L29/45 , H01L21/265 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10808 , H01L27/10817 , H01L29/41775 , H01L29/456
摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.
摘要翻译：具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

54. 发明授权

US5346834A Method for manufacturing a semiconductor device and a semiconductor memory device 失效
标题翻译：半导体装置及半导体存储装置的制造方法
公开(公告)号：US5346834A
公开(公告)日：1994-09-13
申请号：US845063
申请日：1992-03-03
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786 , H01L21/265
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10852 , H01L27/10873 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278 , Y10S148/014
摘要： An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate. Next a gate electrode is formed on silicon island, followed by forming source and drain regions in the silicon island employing the gate electrode as a mask.
摘要翻译：提供了一种用于制造绝缘栅场效应晶体管的改进方法。作为第一步骤，在硅衬底上生长氧化硅膜，并且在其上沉积第一氮化硅膜。然后使用抗蚀剂图案作为掩模来蚀刻第一硅亚硝酸盐膜，氧化硅膜和硅衬底，以形成包括硅衬底的至少一部分的硅岛。然后在通过第二步骤暴露的硅衬底的表面上以及在硅岛的表面上生长第二氧化硅膜，并且在其上沉积第二硅亚硝酸盐膜。然后蚀刻第二硅亚硝酸盐膜以留下沉积在硅岛的侧壁上的第二硅亚硝酸盐膜的一部分。之后，通过硅衬底的表面的热氧化生长第三氧化硅膜，以将硅岛与硅衬底电隔离。接下来，在硅岛上形成栅电极，随后在硅岛中形成源极和漏极区域，采用栅电极作为掩模。

55. 发明授权

US4670768A Complementary MOS integrated circuits having vertical channel FETs 失效
标题翻译：具有垂直沟道FET的互补MOS集成电路
公开(公告)号：US4670768A
公开(公告)日：1987-06-02
申请号：US767794
申请日：1985-08-14
申请人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
发明人： Hideo Sunami , Makoto Ohkura , Shinichiro Kimura
IPC分类号： H01L27/08 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/06 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/786 , H01L27/02 , H01L27/12 , H01L29/06
CPC分类号： H01L29/7827 , H01L21/8221 , H01L21/823885 , H01L27/0688 , H01L27/092 , H01L27/1104 , H01L29/78642
摘要： A semiconductor integrated circuit comprising semiconductor regions in the form of first and second protruding poles that are provided on a semiconductor layer formed on a semiconductor substrate or an insulating substrate, and that are opposed to each other with an insulating region sandwiched therebetween, a p-channel FET provided in the first semiconductor region, and an n-channel FET provided in the second semiconductor region. These FET's have source and drain regions on the upper and bottom portions of the semiconductor regions, and have gate electrodes on the sides of the semiconductor regions. The insulation region between the protruding pole-like semiconductor regions is further utilized as the gate electrode and the gate insulating film.
摘要翻译： PCT No.PCT / JP84 / 00597 Sec。 371日期1985年8月14日 102（e）日期1985年8月14日PCT提交1984年12月14日PCT公布。第WO85 / 02716号公报日期：1985年6月20日。一种半导体集成电路，包括第一和第二突出极的形式的半导体区域，所述半导体区域设置在形成在半导体衬底或绝缘衬底上的半导体层上，并且具有绝缘设置在第一半导体区域中的p沟道FET，以及设置在第二半导体区域中的n沟道FET。这些FET在半导体区域的上部和底部具有源极和漏极区域，并且在半导体区域的侧面上具有栅极电极。突出的柱状半导体区域之间的绝缘区域被进一步用作栅极电极和栅极绝缘膜。

56. 发明申请

US20130051889A1 INPUT DEVICE 审中-公开
标题翻译：输入设备
公开(公告)号：US20130051889A1
公开(公告)日：2013-02-28
申请号：US13598131
申请日：2012-08-29
申请人： Shinichiro Kimura , Shinji Hirano
发明人： Shinichiro Kimura , Shinji Hirano
IPC分类号： B41J5/12
CPC分类号： G06F3/0338
摘要： An input device includes detection parts detecting operation from the outside, a cap member receiving operation from the outside, and an operation part including an operating shaft. The cap member is locked to one end of the operating shaft and a flange portion, which transmits the operation received from the outside, is formed at the other end of the operating shaft. The operating shaft includes an engaging hole formed at one end-side end face of the operating shaft. The cap member includes a first fitting portion having elasticity, and a protruding portion formed at the first fitting portion so as to protrude toward the outside of the cap member. The one end of the operating shaft is press-fitted to the first fitting portion and the protruding portion of the cap member is positioned in the engaging hole, so that the cap member is locked to the operation part.
摘要翻译：输入装置包括从外部检测操作的检测部件，从外部接收操作的帽部件和包括操作轴的操作部。盖构件被锁定到操作轴的一端，并且在操作轴的另一端形成有传递从外部接收的操作的凸缘部。操作轴包括形成在操作轴的一个端侧端面处的接合孔。盖构件包括具有弹性的第一装配部分和形成在第一装配部分上以朝向盖构件的外侧突出的突出部分。操作轴的一端被压配合到第一配合部分，并且帽构件的突出部分位于接合孔中，使得盖构件被锁定到操作部分。

57. 发明授权

US08183115B2 Method of manufacturing a semiconductor device having elevated layers of differing thickness 有权
标题翻译：制造具有不同厚度的升高层的半导体器件的方法
公开(公告)号：US08183115B2
公开(公告)日：2012-05-22
申请号：US13088020
申请日：2011-04-15
申请人： Takashi Ishigaki , Ryuta Tsuchiya , Yusuke Morita , Nobuyuki Sugii , Shinichiro Kimura , Toshiaki Iwamatsu
发明人： Takashi Ishigaki , Ryuta Tsuchiya , Yusuke Morita , Nobuyuki Sugii , Shinichiro Kimura , Toshiaki Iwamatsu
IPC分类号： H01L21/8234
CPC分类号： H01L21/84 , H01L21/26506 , H01L21/26513 , H01L21/76283 , H01L21/823418 , H01L21/823481 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L27/1207
摘要： There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. The first elevated layer is thicker than the second elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided.
摘要翻译：提供了SOI-MISFET，其包括：SOI层; 设置在插入栅极绝缘体的SOI层上的栅电极; 以及第一升高层，其在SOI层上的栅电极的两个侧壁侧的SOI层高于栅电极，从而构成源极和漏极。此外，还提供了一种体MISFET，包括：设置在硅衬底上的栅电极，其插入比SOI MISFET的栅极绝缘体更厚的栅极绝缘体; 以及构造在所述栅电极的两个侧壁处设置在半导体衬底上的源极和漏极的第二升高层。第一升高层比第二升高层厚，并且整个栅电极，SOI-MISFET的源极和漏极的一部分以及体MISFET的源极和漏极的一部分被硅化。

58. 发明授权

US08084810B2 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US08084810B2
公开(公告)日：2011-12-27
申请号：US12648796
申请日：2009-12-29
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L21/336
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

59. 发明申请

US20110039385A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110039385A1
公开(公告)日：2011-02-17
申请号：US12912609
申请日：2010-10-26
申请人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
发明人： Yasuhiro Shimamoto , Digh Hisamoto , Tetsuya Ishimaru , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , G11C16/0425 , H01L21/28282 , H01L21/31155 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/66833
摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.
摘要翻译：提高了包括非易失性存储器的半导体器件的性能和可靠性。非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极存储功能。第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层电介质膜。位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

60. 发明授权

US07847331B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07847331B2
公开(公告)日：2010-12-07
申请号：US11030900
申请日：2005-01-10
申请人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
发明人： Tetsuya Ishimaru , Digh Hisamoto , Kan Yasui , Shinichiro Kimura
IPC分类号： H01L29/792
CPC分类号： G11C16/0466 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.
摘要翻译：在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

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