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51. 发明授权

US06200857B1 Method of manufacturing a semiconductor device without arc loss in peripheral circuit region 有权
标题翻译：在外围电路区域中制造没有电弧损耗的半导体器件的方法
公开(公告)号：US06200857B1
公开(公告)日：2001-03-13
申请号：US09417132
申请日：1999-10-13
申请人： Tommy C. Hsiao , Mark T. Ramsbey , Yu Sun
发明人： Tommy C. Hsiao , Mark T. Ramsbey , Yu Sun
IPC分类号： H01L218247
CPC分类号： H01L27/11526 , H01L27/11541 , Y10S438/981
摘要： Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.
摘要翻译：半导体器件的外围电路区域中的栅电极结构的改进的尺寸精度通过在图案化和离子注入期间避免与芯存储器单元区域中的多个掩模相关联的光致抗蚀剂剥离期间的ARC损耗来实现。实施例包括初始蚀刻以在外围电路区域中形成栅电极结构。随后，通过蚀刻堆叠的栅极电极结构和离子注入来进行核心存储单元区域中的处理，以形成具有光刻胶层的伴随剥离的源极/漏极。

52. 发明授权

US6160317A Method of spacer formation and source protection after self-aligned source formed and a device provided by such a method 有权
标题翻译：自对准源形成后的间隔物形成和源保护方法以及通过这种方法提供的器件
公开(公告)号：US6160317A
公开(公告)日：2000-12-12
申请号：US336057
申请日：1999-06-18
申请人： Yu Sun , Chi Chang , Mark T. Ramsbey
发明人： Yu Sun , Chi Chang , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/088
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.
摘要翻译：本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

53. 发明授权

US6136510A Doubled-sided wafer scrubbing for improved photolithography 失效
标题翻译：双面晶圆洗涤，用于改进光刻
公开(公告)号：US6136510A
公开(公告)日：2000-10-24
申请号：US800940
申请日：1997-02-13
申请人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
发明人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
IPC分类号： G03F7/16 , H01L21/306 , G03F7/00
CPC分类号： G03F7/16 , H01L21/02063
摘要： The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by double-sided scrubbing the wafer prior to photolithography. It was found that particles adhering to the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Double-sided wafer scrubbing removes such adhering particles, thereby improving photolithographic accuracy.
摘要翻译：通过在光刻之前双面擦洗晶片来改善光刻处理的精度，特别是在形成介电层中的小直径通孔和/或沟槽中的精度。发现由先前处理步骤导致的粘附到晶片背面的颗粒导致不精确的光刻处理，特别是在亚微米级。双面晶圆洗涤除去这些粘附颗粒，从而提高光刻精度。

54. 发明授权

US6030868A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译：一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。在多晶硅层上形成多层介电层。蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。

55. 发明授权

US08691647B1 Memory devices containing a high-K dielectric layer 有权
标题翻译：包含高K电介质层的存储器件
公开(公告)号：US08691647B1
公开(公告)日：2014-04-08
申请号：US10927692
申请日：2004-08-27
申请人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
发明人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO2.
摘要翻译：在一个实施例中，公开了一种半导体器件。所述半导体器件形成在具有有源区的半导体衬底上，所述半导体器件包括：栅极电介质层，其设置在所述半导体衬底上，所述栅极电介质层具有至少两个具有至少一个具有电介质的子层的子层常数大于SiO2; 形成在所述栅介质层上的浮置栅极，限定插入在所述半导体衬底的有源区域内形成的源极和漏极之间的沟道; 形成在浮动栅极上方的控制栅极; 以及插入在所述浮置栅极和所述控制栅极之间的隔间介电层，所述栅极间介电层包括：形成在所述浮动栅极上的第一层; 形成在所述第一层上的第二层; 以及形成在第二层上的第三层，其中第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数。

56. 发明申请

US20120038051A1 BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME 有权
标题翻译：带硅胶的局部连接器和其制造方法
公开(公告)号：US20120038051A1
公开(公告)日：2012-02-16
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

57. 发明授权

US07811915B2 Method for forming bit lines for semiconductor devices 有权
标题翻译：用于形成半导体器件的位线的方法
公开(公告)号：US07811915B2
公开(公告)日：2010-10-12
申请号：US12048549
申请日：2008-03-14
申请人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
发明人： Weidong Qian , Mark T. Ramsbey , Tazrien Kamal
IPC分类号： H01L21/22
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A method for forming a semiconductor device includes forming a first dielectric layer over a first portion of a substrate, forming a charge storage layer over the first dielectric layer and etching a trench in the charge storage layer and the first dielectric layer, where the trench extends to the substrate. The method also includes implanting n-type impurities into the substrate to form an n-type region having a first depth and a first width and implanting p-type impurities into the substrate after implanting the n-type impurities, the p-type impurities forming a p-type region having a second depth and a second width. The method further includes forming a second dielectric layer over the charge storage layer and forming a control gate over the second dielectric layer.
摘要翻译：一种形成半导体器件的方法包括在衬底的第一部分上形成第一介电层，在第一介电层上形成电荷存储层，并蚀刻电荷存储层和第一介电层中的沟槽，其中沟槽延伸到基底。该方法还包括将n型杂质注入到衬底中以形成具有第一深度和第一宽度的n型区域，并且在植入n型杂质之后将p型杂质注入到衬底中，形成p型杂质具有第二深度和第二宽度的p型区域。该方法还包括在电荷存储层上形成第二电介质层，并在第二电介质层上形成控制栅极。

58. 发明授权

US07786003B1 Buried silicide local interconnect with sidewall spacers and method for making the same 有权
标题翻译：埋入硅化物与侧壁间隔物的局部互连及其制造方法
公开(公告)号：US07786003B1
公开(公告)日：2010-08-31
申请号：US11136569
申请日：2005-05-25
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L21/4763
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

59. 发明授权

US06969654B1 Flash NVROM devices with UV charge immunity 有权
标题翻译：具有UV电荷免疫功能的闪存NVROM器件
公开(公告)号：US06969654B1
公开(公告)日：2005-11-29
申请号：US09727714
申请日：2000-11-28
申请人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
发明人： Tuan Duc Pham , Mark T. Ramsbey , Jeffrey A. Shields , Angela T. Hui , Dawn Hopper
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8246 , H01L23/552 , H01L27/115
CPC分类号： H01L27/11568 , H01L21/28273 , H01L23/552 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： A method of preventing UV charging of flash NVROM cells during fabrication and a device thereby formed. During device fabrication, a UV blocking layer is deposited over the floating gates. The UV blocking layer substantially blocks UV from entering the gate regions so as to prevent electron mobility sufficient to render the cells unprogrammable or unerasable. The reduced electron migration during processing of the NVROM leads to increased yield and reliability of the devices.
摘要翻译：一种在制造期间防止闪存NVROM单元的紫外线充电的方法和由此形成的装置。在器件制造期间，在阻挡层上沉积UV阻挡层。 UV阻挡层基本上阻止UV进入栅极区域，以便防止电子迁移率足以使电池不可编程或不可擦除。在NVROM处理期间减少的电子迁移导致器件的产量和可靠性的提高。

60. 发明授权

US06927145B1 Bitline hard mask spacer flow for memory cell scaling 有权
标题翻译：位线硬掩模间隔流程用于存储单元缩放
公开(公告)号：US06927145B1
公开(公告)日：2005-08-09
申请号：US10770673
申请日：2004-02-02
申请人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
发明人： Jean Y. Yang , Mark T. Ramsbey , Jaeyong Park , Tazrien Kamal , Emmanuil H. Lingunis
IPC分类号： H01L21/027 , H01L21/761 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11568 , H01L27/115
摘要： The invention is a semiconductor device and a method of forming the semiconductor device. The semiconductor device comprises a substrate; buried bitlines formed in the substrate narrower than achievable at a resolution limit of lithography; a doped region formed adjacent at least one of the buried bitlines; a charge trapping layer disposed over the substrate; and a conductive layer disposed over the charge trapping layer, wherein the doped region adjacent the least one of the buried bitlines inhibits a leakage current between the buried bitlines.
摘要翻译：本发明是半导体器件和形成半导体器件的方法。半导体器件包括衬底; 在衬底中形成的掩埋位线比在光刻的分辨率极限下可实现的更窄; 与所述掩埋位线中的至少一个相邻地形成的掺杂区域; 设置在所述基板上的电荷捕获层; 以及设置在所述电荷俘获层上的导电层，其中与所述掩埋位线中的至少一个相邻的所述掺杂区域抑制所述掩埋位线之间的漏电流。

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