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51. 发明授权

US07376006B2 Enhanced programming performance in a nonvolatile memory device having a bipolar programmable storage element 失效
标题翻译：具有双极可编程存储元件的非易失性存储器件中的增强的编程性能
公开(公告)号：US07376006B2
公开(公告)日：2008-05-20
申请号：US11216518
申请日：2005-08-31
申请人： Johannes Georg Bednorz , John Kenneth DeBrosse , Chung Hon Lam , Gerhard Ingmar Meijer , Jonathan Zanhong Sun
发明人： Johannes Georg Bednorz , John Kenneth DeBrosse , Chung Hon Lam , Gerhard Ingmar Meijer , Jonathan Zanhong Sun
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/79
摘要： A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.
摘要翻译：非易失性存储单元包括可操作地存储存储单元的逻辑状态的双极可编程存储元件和包括第一和第二源极/漏极和栅极的金属氧化物半导体器件。双极可编程存储元件的第一端子适于连接到第一位线。第一源极/漏极连接到双极可编程存储元件的第二端子，第二源极/漏极适于连接到第二位线，并且栅极适于连接到字线。

52. 发明授权

US07351666B2 Layout and process to contact sub-lithographic structures 有权
标题翻译：接触亚光刻结构的布局和工艺
公开(公告)号：US07351666B2
公开(公告)日：2008-04-01
申请号：US11378492
申请日：2006-03-17
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven J. Holmes , David V. Horak , Charles William Koburger, III , Chung Hon Lam
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/76885 , H01L21/76895 , H01L23/528 , H01L2224/06 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method for fabrication includes first and second structures, each including a set of sub-lithographic lines, and contact landing segments connected to at least one of the sub-lithographic lines at an end portion. The first and second structures are nested such that the sub-lithographic lines are disposed in a parallel manner within a width, and the contact landing segments of the first structure are disposed on an opposite side of a length of the sub-lithographic lines relative to the contact landing segments of the second structure. The contact landing segments for the first and second structures are included within the width dimension, wherein the width includes a dimension four times a minimum feature size achievable by lithography.
摘要翻译：一种用于制造的集成电路和方法，包括第一和第二结构，每个结构包括一组子光刻线，以及在端部处连接到至少一个子光刻线的接触着陆段。第一和第二结构被嵌套，使得亚光刻线以平行方式设置在宽度内，并且第一结构的接触着陆段被设置在相对于子平版印刷线的相对侧的相对侧第二结构的接触着陆段。用于第一和第二结构的接触着陆段包括在宽度尺寸内，其中宽度包括通过光刻实现的最小特征尺寸的四倍的尺寸。

53. 发明授权

US06420777B2 Dual layer etch stop barrier 失效
标题翻译：双层蚀刻停止屏障
公开(公告)号：US06420777B2
公开(公告)日：2002-07-16
申请号：US09031251
申请日：1998-02-26
申请人： Chung Hon Lam , Eric Seung Lee , Francis Roger White
发明人： Chung Hon Lam , Eric Seung Lee , Francis Roger White
IPC分类号： H01L2358
CPC分类号： H01L21/0217 , H01L21/022 , H01L21/02271 , H01L21/31116 , H01L21/3185 , Y10S438/97
摘要： A method for reactive ion etching of SiO2 and an etch stop barrier for use in such an etching is provided. A silicon nitride (SixNy) barrier having a Six to Ny ratio (x:y) of less than about 0.8 and preferably the stoichiometric amount of 0.75 provides excellent resilience to positive mobile ion contamination, but poor etch selectivity. However, a silicon nitride barrier having a ratio of Six to Nx (x:y) of 1.0 or greater has excellent etch selectivity with respect to SiO2 but a poor barrier to positive mobile ion contamination. A barrier of silicon nitride is formed on a doped silicon substrate which barrier has two sections. One section has a greater etch selectivity with respect to silicon dioxide than the second section and the second section has a greater resistance to transmission of positive mobile ions than the first section. One section adjacent the silicon substrate has a silicon to nitrogen ratio of less than about 0.8. The second section, formed on top of the first section is formed with the ratio of the silicon to nitrogen of greater than about 0.8. Preferably the two sections together are from about 50 to about 100 nanometers thick.
摘要翻译：提供了用于SiO 2的反应离子蚀刻的方法和用于这种蚀刻中的蚀刻阻挡层。具有小于约0.8且优选化学计量量为0.75的六至奈比（x：y）的氮化硅（SixNy）阻挡层对正移动离子污染提供优异的回弹性，但蚀刻选择性差。然而，六至氮（x：y）的比例为1.0或更大的氮化硅阻挡层相对于SiO 2具有优异的蚀刻选择性，但对于移动离子污染的正面阻挡性差。在掺杂硅衬底上形成氮化硅屏障，该阻挡层具有两个部分。一个部分相对于二氧化硅具有比第二部分更大的蚀刻选择性，并且第二部分比第一部分具有更大的对正性可移动离子透射的抵抗力。与硅衬底相邻的一个部分的硅氮比小于约0.8。在第一部分顶部形成的第二部分形成硅与氮的比大于约0.8。优选地，两个部分一起为约50至约100纳米厚。

54. 发明授权

US06403482B1 Self-aligned junction isolation 失效
标题翻译：自对准结隔离
公开(公告)号：US06403482B1
公开(公告)日：2002-06-11
申请号：US09605726
申请日：2000-06-28
申请人： Nivo Rovedo , Chung Hon Lam
发明人： Nivo Rovedo , Chung Hon Lam
IPC分类号： H01L21302
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/41766
摘要： Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating layer in the bottom of the contact recess; recessing the insulating layer to leave room for a conductive contact layer; depositing the contact layer to make contact on a vertical surface to the Si underneath the gate sidewalls; recessing the contact layer; forming interlayer dielectric and interconnect to complete the circuit.
摘要翻译：在源极/漏极触点下方具有自对准电介质层的晶体管通过构造直到LDD注入的晶体管来形成; 蚀刻对Si和氮化物有选择性的STI氧化物以形成自对准的接触凹部; 在接触凹部的底部沉积绝缘层; 使绝缘层凹陷以留下导电接触层的空间; 沉积接触层以在与栅极侧壁下方的Si的垂直表面上接触; 使接触层凹陷; 形成层间电介质和互连以完成电路。

55. 发明授权

US5656544A Process for forming a polysilicon electrode in a trench 失效
标题翻译：在沟槽中形成多晶硅电极的工艺
公开(公告)号：US5656544A
公开(公告)日：1997-08-12
申请号：US391904
申请日：1995-02-21
申请人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
发明人： Albert Stephan Bergendahl , Claude Louis Bertin , John Edward Cronin , Howard Leo Kalter , Donald McAlpine Kenney , Chung Hon Lam , Hsing-San Lee
IPC分类号： H01L27/10 , H01L21/8239 , H01L21/8242 , H01L21/8247 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/44 , H01L21/48
CPC分类号： H01L29/7882 , H01L27/105 , H01L27/1052 , H01L27/10829 , H01L27/115
摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.
摘要翻译：公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。本发明的阵列提供高密度影子RAM。还公开了用于制造本发明的装置的方法。

56. 发明授权

US08589320B2 Area efficient neuromorphic system that connects a FET in a diode configuration, and a variable resistance material to junctions of neuron circuit blocks 有权
标题翻译：将二极管配置中的FET和可变电阻材料连接到神经元电路块的结的区域有效的神经元系统
公开(公告)号：US08589320B2
公开(公告)日：2013-11-19
申请号：US13548532
申请日：2012-07-13
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06E1/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic system includes a plurality of synapse blocks electrically connected to a plurality of neuron circuit blocks. The plurality of synapse blocks includes a plurality of neuromorphic circuits. Each neuromorphic circuit includes a field effect transistor in a diode configuration electrically connected to variable resistance material, where the variable resistance material provides a programmable resistance value. Each neuromorphic circuit also includes a first junction electrically connected to the variable resistance material and an output of one or more of the neuron circuit blocks, and a second junction electrically connected to the field effect transistor and an input of one or more of the neuron circuit blocks.
摘要翻译：神经元系统包括电连接到多个神经元电路块的多个突触块。多个突触块包括多个神经形态电路。每个神经形态电路包括电连接到可变电阻材料的二极管配置中的场效应晶体管，其中可变电阻材料提供可编程电阻值。每个神经形态电路还包括电连接到可变电阻材料的第一结和一个或多个神经元电路块的输出，以及电连接到场效应晶体管的第二结和一个或多个神经元电路的输入块。

57. 发明授权

US08350316B2 Phase change memory cells having vertical channel access transistor and memory plane 有权
标题翻译：具有垂直通道存取晶体管和存储器平面的相变存储单元
公开(公告)号：US08350316B2
公开(公告)日：2013-01-08
申请号：US12471287
申请日：2009-05-22
申请人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
发明人： Hsiang-Lan Lung , Chung Hon Lam , Ming-Hsiu Lee , Bipin Rajendran
IPC分类号： H01L29/732
CPC分类号： H01L27/101 , G11C13/0004 , H01L27/2454 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.
摘要翻译：描述存储器件以及制造方法。如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的相应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻多行字线中的字线。相应的字线用作场效应晶体管的栅极。电介质将对应的字线与沟道区分开。存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

58. 发明申请

US20120327708A1 HIGH-ENDURANCE PHASE CHANGE MEMORY DEVICES AND METHODS FOR OPERATING THE SAME 有权
标题翻译：高耐久性相变记忆体装置及其操作方法
公开(公告)号：US20120327708A1
公开(公告)日：2012-12-27
申请号：US13472395
申请日：2012-05-15
申请人： Pei-Ying DU , Chao-I Wu , Ming-Hsiu Lee , Sangbum Kim , Chung Hon Lam
发明人： Pei-Ying DU , Chao-I Wu , Ming-Hsiu Lee , Sangbum Kim , Chung Hon Lam
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0021
摘要： Phase change based memory devices and methods for operating such devices described herein overcome the set or reset failure mode and result in improved endurance, reliability and data storage performance. A high current repair operation is carried out in response to a set or reset failure of a phase change memory cell. The higher current repair operation can provide a sufficient amount of energy to reverse compositional changes in the phase change material which can occur after repeated set and reset operations. By reversing these compositional changes, the techniques described herein can recover a memory cell which experienced a set or reset failure, thereby extending the endurance of the memory cell. In doing so, phase change based memory devices and methods for operating such devices are provided which have high cycle endurance.
摘要翻译：基于相变的存储器件和用于操作这里描述的这种器件的方法克服了设置或复位故障模式并导致改进的耐久性，可靠性和数据存储性能。响应于相变存储单元的置位或复位故障执行高电流修复操作。更高的电流修复操作可以提供足够的能量来反转在重复设置和复位操作之后可能发生的相变材料的组成变化。通过颠倒这些组合变化，本文描述的技术可以恢复经历设置或复位故障的存储器单元，从而延长存储单元的耐久性。这样做，提供了具有高循环耐久性的基于相变的存储器件和用于操作这些器件的方法。

59. 发明授权

US08311965B2 Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material 有权
标题翻译：使用场效应晶体管（FET）和可变电阻材料的区域效率的神经元电路
公开(公告)号：US08311965B2
公开(公告)日：2012-11-13
申请号：US12620624
申请日：2009-11-18
申请人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
发明人： Matthew J. Breitwisch , Chung Hon Lam , Dharmendra S. Modha , Bipin Rajendran
IPC分类号： G06F17/00
CPC分类号： G06N3/0635 , G11C11/54 , G11C13/0002 , H01L27/285
摘要： A neuromorphic circuit includes a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor. The neuromorphic circuit also includes a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor. The neuromorphic circuit further includes variable resistance material electrically connected to both the first drain and the second drain, where the variable resistance material provides a programmable resistance value. The neuromorphic circuit additionally includes a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit, and a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.
摘要翻译：神经形态电路包括在第一二极管配置中建立第一场效应晶体管的第一栅极和第一漏极之间的电连接的第一场效应晶体管。神经形态电路还包括在第二二极管配置中建立第二场效应晶体管的第二栅极和第二漏极之间的电连接的第二场效应晶体管。神经形态电路还包括电连接到第一漏极和第二漏极的可变电阻材料，其中可变电阻材料提供可编程电阻值。神经形态电路还包括电连接到可变电阻材料并且提供到神经元电路的输出的第一连接点的第一结，以及电连接到可变电阻材料并且提供第二连接点到第二连接点的第二连接点神经元电路。

60. 发明授权

US08115186B2 Phase change memory cell with reduced switchable volume 有权
标题翻译：相变容量小的相变存储单元
公开(公告)号：US08115186B2
公开(公告)日：2012-02-14
申请号：US12498840
申请日：2009-07-07
申请人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
发明人： Matthew J. Breitwisch , Roger W. Cheek , Eric Andrew Joseph , Chung Hon Lam , Hsiang-Lan Lung , Alejandro Gabriel Schrott
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L45/144 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1666
摘要： A memory cell is fabricated by forming a dielectric layer and patterning a hole in the dielectric layer. Patterning the hole is accomplished at least in part by contacting the dielectric layer with a catalytic material in the presence of a reactant under conditions effective to remove those areas of the dielectric layer in contact with the catalytic material. A phase change feature is then formed in contact with the dielectric layer such that a portion of the phase change feature at least partially fills the hole in the dielectric layer. At least a portion of the patterned dielectric layer remains in the ultimate memory cell.
摘要翻译：通过形成电介质层并在电介质层中构图孔来制造存储单元。至少部分地通过在有效去除与催化材料接触的电介质层的那些区域的条件下在反应物存在下使介电层与催化材料接触来对孔进行图案化。然后形成与电介质层接触的相变特征，使得相变特征的一部分至少部分地填充介电层中的孔。图案化介电层的至少一部分保留在最终存储单元中。

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