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51. 发明申请

US20050156629A1 HIGH CURRENT 5V TOLERANT BUFFER USING A 2.5 VOLT POWER SUPPLY 失效
标题翻译：使用2.5伏电源的高电流5V耐受缓冲器
公开(公告)号：US20050156629A1
公开(公告)日：2005-07-21
申请号：US10759253
申请日：2004-01-20
申请人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
发明人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： Using at best a 2.5V nominal power supply, 3.3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2.5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors the inverter are tied together and driven by an applied signal.
摘要翻译：最多使用2.5V标称电源，3.3V技术可用于实现5V容限的开漏输出缓冲器。仅使用2.5V电源即可实现高电压和/或电流公差。 p沟道FET晶体管连接在电源和节点之间，而节点又连接到两个串联输出FET晶体管之间的节点。第一晶体管连接在PAD和节点之间，第二晶体管连接在节点和地之间。第二晶体管的栅极由形成在p沟道FET晶体管的串联串和n沟道FET晶体管之间的另一个节点驱动。第一晶体管的另一侧连接到电源，第二晶体管的另一侧连接到地。晶体管的栅极将反相器连接在一起并由施加的信号驱动。

52. 发明授权

US08847657B2 Low power receiver for implementing a high voltage interface implemented with low voltage devices 有权
标题翻译：低功率接收器，用于实现采用低电压器件实现的高压接口
公开(公告)号：US08847657B2
公开(公告)日：2014-09-30
申请号：US13530426
申请日：2012-06-22
申请人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译：一种包括第一级和第二级的装置。第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。第二级可以被配置为响应于第一电压而产生核心电压。从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。

53. 发明授权

US08487691B1 AC noise suppression from a bias signal in high voltage supply/low voltage device 有权
标题翻译：高压电源/低压器件偏置信号的交流噪声抑制
公开(公告)号：US08487691B1
公开(公告)日：2013-07-16
申请号：US13494282
申请日：2012-06-12
申请人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
IPC分类号： G05F1/10
CPC分类号： H03F1/26 , H03F3/2171 , H03K19/00346
摘要： An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first control voltage and a second control voltage. The second circuit may be configured to generate a bias signal in response to the first control voltage and the second control voltage. The third circuit may be configured to generate a filtered signal in response to the bias signal. The filtered signal may be added to the first control voltage and the second control voltage to provide AC noise suppression when generating the bias signal.
摘要翻译：一种包括第一电路，第二电路和第三电路的装置。第一电路可以被配置为产生第一控制电压和第二控制电压。第二电路可以被配置为响应于第一控制电压和第二控制电压而产生偏置信号。第三电路可以被配置为响应于偏置信号产生滤波信号。滤波后的信号可以被添加到第一控制电压和第二控制电压，以在产生偏置信号时提供AC噪声抑制。

54. 发明授权

US5847556A Precision current source 失效
标题翻译：精密电流源
公开(公告)号：US5847556A
公开(公告)日：1998-12-08
申请号：US994019
申请日：1997-12-18
申请人： Makeshwar Kothandaraman , Bijit Thakorbhai Patel , David Arthur Rich
发明人： Makeshwar Kothandaraman , Bijit Thakorbhai Patel , David Arthur Rich
IPC分类号： G05F3/26 , H03F3/343 , G05F3/16
CPC分类号： G05F3/262
摘要： A current source includes a first current mirror and a second current mirror that share a common current path. The current in the common current path mirrors a current of a current reference connected to the first current mirror. A current in an output current path of the second current mirror mirrors the current of the common current path. A first feedback loop controls the current in the common current path and a second feedback loop matches a voltage of the common current path with an output voltage. The cooperation of the first and second feedback loops ensures that the output current replicates the current of the current reference even when an voltage of the current source is close to the supply voltage. Thus, the voltage swing of the current source output voltage is increased and a precision current source is provided even when the output voltage is close to the supply voltage.
摘要翻译：电流源包括共享公共电流路径的第一电流镜和第二电流镜。公共电流通路中的电流反映连接到第一电流镜的电流基准的电流。第二电流镜的输出电流路径中的电流反映了公共电流路径的电流。第一反馈环路控制公共电流路径中的电流，第二反馈环路将公共电流路径的电压与输出电压相匹配。第一和第二反馈回路的协作确保即使当电流源的电压接近电源电压时，输出电流复制电流参考电流。因此，即使当输出电压接近电源电压时，电流源输出电压的电压摆幅也增加，并提供精确的电流源。

55. 发明授权

US08803535B2 Impedance mismatch detection circuit 有权
标题翻译：阻抗失配检测电路
公开(公告)号：US08803535B2
公开(公告)日：2014-08-12
申请号：US13171725
申请日：2011-06-29
申请人： Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
发明人： Makeshwar Kothandaraman , Pankaj Kumar , Pramod Parameswaran
IPC分类号： G01R27/26 , H03F3/45
CPC分类号： H03F3/45475 , H03F2203/45594
摘要： A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored.
摘要翻译：用于检测待监测电路中的上拉和下拉器件之间的阻抗失配的比较电路包括一个比较器，用于接收第一和第二信号，并产生一个第三信号，该第三信号指示第一和第二信号之间的差值和第二信号。第一信号发生器用于产生表示参考上拉和下拉电流之间的差的第一信号，该下拉电流被缩放规定量。参考上拉电流指示流过待监测电路中的至少一个对应的上拉晶体管器件的电流。下拉参考电流表示流过待监测电路中的至少一个对应的下拉晶体管器件的电流。与比较器的第二输入端连接的第二信号发生器可操作以产生第二信号作为参考电压，该参考电压限定与待监视电路相关联的规定阻抗失配阈值。

56. 发明申请

US20130342258A1 LOW POWER RECEIVER FOR IMPLEMENTING A HIGH VOLTAGE INTERFACE IMPLEMENTED WITH LOW VOLTAGE DEVICES 有权
标题翻译：用于实现低电压设备实现的高电压接口的低功率接收器
公开(公告)号：US20130342258A1
公开(公告)日：2013-12-26
申请号：US13530426
申请日：2012-06-22
申请人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
发明人： Pankaj Kumar , Pramod Parameswaran , Vani Deshpande , Makeshwar Kothandaraman
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K19/0013 , H03K19/018507
摘要： An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
摘要翻译：一种包括第一级和第二级的装置。第一级可以被配置为响应于具有从焊盘接收到的第二电压的输入信号而产生具有第一电压的中间信号。第二级可以被配置为响应于第一电压而产生核心电压。从焊盘接收的电压可以在符合一个或多个公布的接口规范的电压下工作。

57. 发明申请

US20120326745A1 Current-Mode Logic Buffer with Enhanced Output Swing 有权
标题翻译：具有增强输出摆幅的电流模式逻辑缓冲器
公开(公告)号：US20120326745A1
公开(公告)日：2012-12-27
申请号：US13165500
申请日：2011-06-21
申请人： Makeshwar Kothandaraman , Pankaj Kumar , Paul K. Hartley , John Christopher Kriz
发明人： Makeshwar Kothandaraman , Pankaj Kumar , Paul K. Hartley , John Christopher Kriz
IPC分类号： H03K19/003 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/09432 , H03K19/018528
摘要： A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off.
摘要翻译：具有增加的输出电压摆幅的差分缓冲电路包括至少包括第一和第二晶体管的差分输入级，第一和第二晶体管分别用于接收第一和第二信号。缓冲电路还包括连接在差分输入级与第一电压源之间的偏置级。偏置级用于产生作为提供给偏置级的第三信号的函数的静态电流。负载电路连接在第二电压源和差分输入级之间，缓冲电路的第一和第二差分输出在负载电路和差分输入级之间的结点处产生。负载电路分别包括与第一和第二晶体管耦合的第一和第二开关元件。当第一晶体管截止时，第一开关元件可操作以将第一差分输出电连接到第二电压源。当第二晶体管截止时，第二开关元件可操作以将第二差分输出电连接到第二电压源。

58. 发明授权

US07002372B2 Moderate current 5V tolerant buffer using a 2.5 volt power supply 有权
标题翻译：使用2.5伏电源的中等电流5V容限缓冲器
公开(公告)号：US07002372B2
公开(公告)日：2006-02-21
申请号：US10759162
申请日：2004-01-20
申请人： Carol Ann Huber , Bernard Lee Morris , Makeshwar Kothandaraman , Yehuda Smooha
发明人： Carol Ann Huber , Bernard Lee Morris , Makeshwar Kothandaraman , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00315 , H03K19/018521
摘要： A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.
摘要翻译：具有中等电流公差能力的低电压，5V容限开漏输出缓冲器采用3.3V技术，使用2.5V或更小的额定电源。缓冲器包括反相器，三个n沟道FET晶体管的电流路径的串联连接和背栅偏置发生器。三个晶体管的串联连接的一个端子连接到PAD，并且该串联的下部晶体管的另一个端子连接到地。偏置发生器使用在VDD和PAD之间交叉连接的两个p沟道场效应晶体管（FET）形成。三个晶体管的中心一个的栅极连接到电源。偏置发生器的输出端连接到上部晶体管的栅极。本发明的缓冲器可以使用标准的3.3V工艺制造，但是功率为例如2.5V或1.8V的电源。

59. 发明授权

US6107882A Amplifier having improved common mode voltage range 失效
标题翻译：具有改善的共模电压范围的放大器
公开(公告)号：US6107882A
公开(公告)日：2000-08-22
申请号：US65255
申请日：1998-04-23
申请人： Thaddeus John Gabara , Makeshwar Kothandaraman , Bijit Thakorbhai Patel
发明人： Thaddeus John Gabara , Makeshwar Kothandaraman , Bijit Thakorbhai Patel
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45237 , H03F3/45479 , H03F3/4565 , H03F3/45659 , H03F2203/45352 , H03F2203/45371 , H03F2203/45418 , H03F2203/45424
摘要： Embodiments of the invention include an amplifier such as a differential amplifier having an improved common mode voltage range (CMVR). The amplifier includes a translator coupled to a second stage amplifying circuitry wherein the translator uses feedback and a parallel connection of input devices to improve the common mode voltage range of the amplifier while providing for enablement of the circuit functionality. The translator uses parallel connections of N-channel and P-channel devices such as transistors to extract alternating current (ac) signals riding on a common mode voltage and to translate the extracted ac signals to ride on a constant reference voltage (V.sub.ref). The translated signals are then amplified in a conventional manner, such as by a gate thresholding or a self-biasing technique. An input sensing circuit within the translator provides an offset detection signal to a correction circuit, also within the translator. The correction circuit compares the signal with an applied reference signal (V.sub.ref) and, based thereon, applies a correction signal to the input sensing circuit. With the benefit of such correction signals, the input sensing circuit translates an input signal with a large common mode voltage range to an output signal that rides on the dc voltage that is approximately equal to the reference signal, V.sub.ref.
摘要翻译：本发明的实施例包括具有改进的共模电压范围（CMVR）的诸如差分放大器的放大器。放大器包括耦合到第二级放大电路的转换器，其中转换器使用反馈和输入装置的并联连接来改善放大器的共模电压范围，同时提供电路功能的实现。转换器使用N沟道和P沟道器件（例如晶体管）的并联连接来提取乘以共模电压的交流（ac）信号，并将提取的交流信号转换为乘以恒定参考电压（Vref）。然后，以常规方式，例如通过门限阈值或自偏置技术来放大转换后的信号。翻译器内的输入感测电路还向翻译器内的校正电路提供偏移检测信号。校正电路将信号与施加的参考信号（Vref）进行比较，并且基于此，将校正信号施加到输入感测电路。利用这种校正信号，输入感测电路将具有大共模电压范围的输入信号转换成乘以大约等于参考信号Vref的直流电压的输出信号。

60. 发明授权

US5963083A CMOS reference voltage generator 失效
标题翻译： CMOS参考电压发生器
公开(公告)号：US5963083A
公开(公告)日：1999-10-05
申请号：US067818
申请日：1998-04-28
申请人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
发明人： Makeshwar Kothandaraman , Bernard Lee Morris , Bijit Thakorbhai Patel , Wayne E. Werner
IPC分类号： G05F3/24 , H03K17/08 , H03K19/003 , G05F1/10
CPC分类号： G05F3/247
摘要： A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at "hot pluggable" condition), the voltage generator is configured to maintain a "protection" output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.
摘要翻译： CMOS电压发生器，用于提供参考电压VDD2，只要存在电源，该参考电压VDD2将跟踪低电平电源电压VDD（约3.0V-3.6V）。当VDD不存在（定义为“可热插拔”状态）时，电压发生器被配置为保持“保护”输出电压小于沿电路信号总线出现的较高电压（约5V）。特别地，该电路包括设置在信号总线与输出电压端子之间的至少一对二极管连接的N沟道器件，以提供必要的保护。

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