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1. 发明申请

US20050156629A1 HIGH CURRENT 5V TOLERANT BUFFER USING A 2.5 VOLT POWER SUPPLY 失效
标题翻译：使用2.5伏电源的高电流5V耐受缓冲器
公开(公告)号：US20050156629A1
公开(公告)日：2005-07-21
申请号：US10759253
申请日：2004-01-20
申请人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
发明人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： Using at best a 2.5V nominal power supply, 3.3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2.5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors the inverter are tied together and driven by an applied signal.
摘要翻译：最多使用2.5V标称电源，3.3V技术可用于实现5V容限的开漏输出缓冲器。仅使用2.5V电源即可实现高电压和/或电流公差。 p沟道FET晶体管连接在电源和节点之间，而节点又连接到两个串联输出FET晶体管之间的节点。第一晶体管连接在PAD和节点之间，第二晶体管连接在节点和地之间。第二晶体管的栅极由形成在p沟道FET晶体管的串联串和n沟道FET晶体管之间的另一个节点驱动。第一晶体管的另一侧连接到电源，第二晶体管的另一侧连接到地。晶体管的栅极将反相器连接在一起并由施加的信号驱动。

2. 发明申请

US20060192587A1 Self-bypassing voltage level translator circuit 有权
公开(公告)号：US20060192587A1
公开(公告)日：2006-08-31
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.

3. 发明申请

US20070075748A1 Floating well circuit having enhanced latch-up performance 失效
公开(公告)号：US20070075748A1
公开(公告)日：2007-04-05
申请号：US11239840
申请日：2005-09-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Duane Loeper , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Duane Loeper , Bernard Morris , Yehuda Smooha
IPC分类号： H03K5/22
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.

4. 发明申请

US20070046338A1 Buffer circuit with multiple voltage range 失效
标题翻译：具有多电压范围的缓冲电路
公开(公告)号：US20070046338A1
公开(公告)日：2007-03-01
申请号：US11215663
申请日：2005-08-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Bernard Morris , Yehuda Smooha
IPC分类号： H03B1/00
CPC分类号： H03K19/018585 , H03K19/018521 , H03K19/018592
摘要： A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of the first buffer connects to an external pad of the buffer circuit, and an output of the second buffer connects to the pad via the isolation circuit. The buffer circuit is selectively operative in at least a first mode or a second mode in response to at least a first control signal. The isolation circuit is operative in the first mode to substantially isolate the second buffer from the external pad and is operative in the second mode to connect the output of the second buffer to the external pad.
摘要翻译：在多个电源电压电平下工作的缓冲电路包括第一和第二缓冲器，第一缓冲器被配置为与第一电压源一起操作，第二缓冲器与第二电压源一起工作。缓冲电路还包括可控隔离电路。第一缓冲器的输出连接到缓冲电路的外部焊盘，第二缓冲器的输出经由隔离电路连接到焊盘。响应于至少第一控制信号，缓冲器电路以至少第一模式或第二模式选择性地工作。隔离电路在第一模式下工作，以将第二缓冲器与外部焊盘基本隔离，并且在第二模式下工作，以将第二缓冲器的输出连接到外部焊盘。

5. 发明申请

US20100271118A1 I/O Buffer with Low Voltage Semiconductor Devices 失效
标题翻译：带低压半导体器件的I / O缓冲器
公开(公告)号：US20100271118A1
公开(公告)日：2010-10-28
申请号：US12428556
申请日：2009-04-23
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John Kriz , Jeffrey Nagy , Yehuda Smooha , Pankaj Kumar
IPC分类号： G05F1/10
CPC分类号： H03K17/0822 , H03K19/018528
摘要： Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output (“I/O”) buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.
摘要翻译：所描述的实施例提供了用于保护具有第一和第二I / O晶体管的输入/输出（“I / O”）缓冲器的DC和瞬态过电压状态。第一I / O晶体管耦合到适于防止至少第一I / O晶体管上的过电压状态的第一过电压保护电路。第二I / O晶体管耦合到适于防止至少第二I / O晶体管上的过电压状态的第二过电压保护电路。从缓冲器的工作电压产生第一和第二偏置电压。从i）第一偏置电压产生第三偏置电压，或者ii）缓冲器的输出信号电压，以及从i）第二偏置电压产生第四偏置电压，或ii）输出信号电压缓冲。第三和第四偏置电压分别提供给第一和第二过压保护电路。

6. 发明申请

US20080074171A1 Method and Apparatus for Improving Reliability of an Integrated Circuit Having Multiple Power Domains 有权
标题翻译：提高具有多个电源域的集成电路的可靠性的方法和装置
公开(公告)号：US20080074171A1
公开(公告)日：2008-03-27
申请号：US11535198
申请日：2006-09-26
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： G05F1/10
CPC分类号： H03K19/0016 , H01L27/0251 , H03K19/00315
摘要： An IC having improved reliability includes at least first and second circuit blocks and at least first and second power domains, the first circuit block being connected to the first power domain and the second circuit block being connected to the second power domain. The IC further includes at least one control circuit configured to generate at least first and second control signals. The first control signal is operative to selectively connect the first power domain to a first voltage supply, and the second control signal is operative to selectively connect the second power domain to a second voltage supply. The IC includes at least first and second clamp circuits, the first clamp circuit being connected to the first power domain, the second clamp circuit being connected to the second power domain. Each of the clamp circuits is operative to prevent a voltage on a corresponding power domain from rising above a prescribed voltage level for the corresponding power domain.
摘要翻译：具有改进的可靠性的IC至少包括第一和第二电路块以及至少第一和第二电力域，第一电路块连接到第一电力域，第二电路块连接到第二电力域。 IC还包括被配置为产生至少第一和第二控制信号的至少一个控制电路。第一控制信号用于选择性地将第一功率域连接到第一电压源，并且第二控制信号用于选择性地将第二功率域连接到第二电压源。 IC包括至少第一和第二钳位电路，第一钳位电路连接到第一电源域，第二钳位电路连接到第二电源域。每个钳位电路可操作以防止相应功率域上的电压升高到对应功率域的规定电压电平以上。

7. 发明授权

US07276957B2 Floating well circuit having enhanced latch-up performance 失效
标题翻译：具有增强的闭锁性能的浮动井回路
公开(公告)号：US07276957B2
公开(公告)日：2007-10-02
申请号：US11239840
申请日：2005-09-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Duane J. Loeper , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： A circuit for defining a voltage potential of a floating well in which is formed at least one metal-oxide-semiconductor device includes a sense circuit operative to detect a voltage at a node to which the floating well is connected and to generate a control signal indicative of whether the voltage at the node is substantially within a voltage range. A lower value of the voltage range is substantially equal to a threshold voltage below a first supply voltage of the circuit. An upper value of the voltage range is substantially equal to a threshold voltage above the first supply voltage. The circuit for defining the voltage potential of the floating well further includes a voltage generator circuit operative to receive the control signal and to generate a bias signal for setting a voltage potential of the well in response to the control signal, the bias signal being controlled throughout the voltage range.
摘要翻译：用于限定其中形成有至少一个金属氧化物半导体器件的浮动阱的电压电位的电路包括感测电路，其可操作以检测浮动阱连接到的节点处的电压，并产生指示性的控制信号节点处的电压是否基本上在电压范围内。电压范围的较低值基本上等于低于电路的第一电源电压的阈值电压。电压范围的较高值基本上等于高于第一电源电压的阈值电压。用于定义浮动阱的电压电位的电路还包括电压发生器电路，其操作以接收控制信号并产生用于响应于控制信号设置阱的电压电位的偏置信号，偏置信号被控制在整个电压范围。

8. 发明授权

US08089739B2 Electrostatic discharge protection circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US08089739B2
公开(公告)日：2012-01-03
申请号：US12438460
申请日：2007-10-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H3/22 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0266
摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。第二电压供应节点可操作以接收小于第一电压的第二电压。第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

9. 发明授权

US07145364B2 Self-bypassing voltage level translator circuit 有权
标题翻译：自我旁路电压电平转换电路
公开(公告)号：US07145364B2
公开(公告)日：2006-12-05
申请号：US11065785
申请日：2005-02-25
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K3/012 , H03K3/356113 , H03K17/102
摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.
摘要翻译：响应于控制信号，电压电平转换器电路可选择性地以至少两种模式之一工作。在第一模式中，电压电平转换器电路用于将提供第一电压的参考第一源的输入信号转换为参考提供第二电压的第二源的输出信号。在第二模式中，电压电平转换器电路用于提供从电压转换器电路的输入到其输出的信号路径，而不转换输入信号。控制信号表示第一电压和第二电压之间的差。

10. 发明授权

US07002372B2 Moderate current 5V tolerant buffer using a 2.5 volt power supply 有权
标题翻译：使用2.5伏电源的中等电流5V容限缓冲器
公开(公告)号：US07002372B2
公开(公告)日：2006-02-21
申请号：US10759162
申请日：2004-01-20
申请人： Carol Ann Huber , Bernard Lee Morris , Makeshwar Kothandaraman , Yehuda Smooha
发明人： Carol Ann Huber , Bernard Lee Morris , Makeshwar Kothandaraman , Yehuda Smooha
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00315 , H03K19/018521
摘要： A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.
摘要翻译：具有中等电流公差能力的低电压，5V容限开漏输出缓冲器采用3.3V技术，使用2.5V或更小的额定电源。缓冲器包括反相器，三个n沟道FET晶体管的电流路径的串联连接和背栅偏置发生器。三个晶体管的串联连接的一个端子连接到PAD，并且该串联的下部晶体管的另一个端子连接到地。偏置发生器使用在VDD和PAD之间交叉连接的两个p沟道场效应晶体管（FET）形成。三个晶体管的中心一个的栅极连接到电源。偏置发生器的输出端连接到上部晶体管的栅极。本发明的缓冲器可以使用标准的3.3V工艺制造，但是功率为例如2.5V或1.8V的电源。

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