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51. 发明申请

US20070212872A1 Single mask process for variable thickness dual damascene structures, other grey-masking processes, and structures made using grey-masking 审中-公开
标题翻译：用于可变厚度双镶嵌结构，其他灰度掩蔽工艺和使用灰色掩蔽制成的结构的单掩模工艺
公开(公告)号：US20070212872A1
公开(公告)日：2007-09-13
申请号：US11748269
申请日：2007-05-14
申请人： Timothy Daubenspeck , Jeffrey Gambino , Kevin Ostrowski , Wolfgang Sauter
发明人： Timothy Daubenspeck , Jeffrey Gambino , Kevin Ostrowski , Wolfgang Sauter
IPC分类号： H01L21/4763 , H01L21/266
CPC分类号： H01L21/31144 , G03F1/50 , H01L21/3083 , H01L21/32139 , H01L21/76807 , H01L21/76808 , H01L21/76816 , H01L21/76885 , H01L2221/1021
摘要： By using a multiple grey tone mask with at least two greys in semiconductor manufacture, multiple wiring thicknesses can now be made in a single level where previously only one wiring thickness could be provided. For example, power and signal wires of different thicknesses in a single layer can be provided.
摘要翻译：通过在半导体制造中使用具有至少两个灰度的多灰度蒙版掩模，现在可以在单一级别中进行多个布线厚度，其中先前只能提供一个布线厚度。例如，可以提供单层中不同厚度的功率和信号线。

52. 发明申请

US20070108485A1 IMAGE SENSOR CELLS 失效
标题翻译：图像传感器细胞
公开(公告)号：US20070108485A1
公开(公告)日：2007-05-17
申请号：US11619024
申请日：2007-01-02
申请人： James Adkisson , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Richard Rassel
发明人： James Adkisson , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Richard Rassel
IPC分类号： H01L31/113 , H01L21/00
CPC分类号： H01L27/14609 , H01L27/1463 , H01L27/14641 , H01L27/14643 , H01L31/035281
摘要： A structure (and method for forming the same) for an image sensor cell. The method includes providing a semiconductor substrate. Then, a charge collection well is formed in the semiconductor substrate, the charge collection well comprising dopants of a first doping polarity. Next, a surface pinning layer is formed in the charge collection well, the surface pinning layer comprising dopants of a second doping polarity opposite to the first doping polarity. Then, an electrically conductive push electrode is formed in direct physical contact with the surface pinning layer but not in direct physical contact with the charge collection well. Then, a transfer transistor is formed on the semiconductor substrate. The transfer transistor includes first and second source/drain regions and a channel region. The first and second source/drain regions comprise dopants of the first doping polarity. The first source/drain region is in direct physical contact with the charge collection well.
摘要翻译：用于图像传感器单元的结构（及其形成方法）。该方法包括提供半导体衬底。然后，在半导体衬底中形成电荷收集阱，电荷收集阱包含第一掺杂极性的掺杂剂。接下来，在电荷收集阱中形成表面钉扎层，表面钉扎层包括与第一掺杂极性相反的第二掺杂极性的掺杂剂。然后，导电的推动电极形成为与表面钉扎层直接物理接触，但不与电荷收集阱直接物理接触。然后，在半导体衬底上形成传输晶体管。传输晶体管包括第一和第二源极/漏极区域和沟道区域。第一和第二源/漏区包括第一掺杂极性的掺杂剂。第一源极/漏极区域与电荷收集阱直接物理接触。

53. 发明申请

US20070013071A1 PROBING PADS IN KERF AREA FOR WAFER TESTING 失效
标题翻译：在KERF区域进行水分测试的探针垫
公开(公告)号：US20070013071A1
公开(公告)日：2007-01-18
申请号：US11160461
申请日：2005-06-24
申请人： James Adkisson , Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
发明人： James Adkisson , Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L22/32 , H01L22/34 , H01L24/06 , H01L2224/05624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14 , H01L2924/00014
摘要： A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.
摘要翻译：一种结构及其形成方法。该结构包括（a）具有顶部衬底表面的衬底; （b）在顶部衬底表面上的集成电路，其中所述集成电路包括电连接到所述集成电路的晶体管的接合焊盘; （c）在顶部基板表面上和集成电路的周边上的保护环; （c）顶部衬底表面上的切口区域，其中所述保护环夹在所述集成电路和所述切口区域之间并物理隔离所述集成电路和所述切口区域，其中所述切口区域包括电连接到所述接合焊盘的探针焊盘，并且其中所述切口区域适用于通过芯片切割而损坏，而不会损坏集成电路和保护环。

54. 发明申请

US20060016861A1 Damascene patterning of barrier layer metal for C4 solder bumps 失效
公开(公告)号：US20060016861A1
公开(公告)日：2006-01-26
申请号：US10710562
申请日：2004-07-21
申请人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
发明人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
IPC分类号： B23K31/02
CPC分类号： H01L24/12 , B23K3/0623 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05006 , H01L2224/05017 , H01L2224/05546 , H01L2224/05556 , H01L2224/05557 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13006 , H01L2224/131 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , Y10T29/49144 , H01L2224/13099
摘要： A system and method for forming a novel C4 solder bump for BLM (Ball Limiting Metallurgy) includes a novel damascene technique is implemented to eliminate the Cu undercut problem and improve the C4 pitch. In the process, a barrier layer metal stack is deposited above a metal pad layer. A top layer of the barrier layer metals (e.g., Cu) is patterned by CMP. Only bottom layers of the barrier metal stack are patterned by a wet etching. The wet etch time for the Cu-based metals is greatly reduced resulting in a reduced undercut. This allows the pitch of the C4 solder bumps to be reduced. An alternate method includes use of multiple vias at the solder bump terminal.

55. 发明授权

US06261950B1 Self-aligned metal caps for interlevel metal connections 有权
标题翻译：用于层间金属连接的自对准金属盖
公开(公告)号：US06261950B1
公开(公告)日：2001-07-17
申请号：US09420402
申请日：1999-10-18
申请人： Dirk Tobben , Jeffrey Gambino
发明人： Dirk Tobben , Jeffrey Gambino
IPC分类号： H01L214763
CPC分类号： H01L23/5226 , H01L21/76886 , H01L2924/0002 , H01L2924/00
摘要： A method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A cap metal is selectively depositing on the metal structure such that the cap metal is deposited only on the metal structure. A second dielectric layer is formed over the cap metal. The second dielectric layer is opened to form a via terminating in the cap metal. A conductive material is deposited in the via to provide a contact to the metal structure through the cap metal.
摘要翻译：根据本发明的用于连接具有自对准金属盖的金属结构的方法包括在第一电介质层中提供金属结构。金属结构和第一介电层共享基本平坦的表面。帽金属选择性地沉积在金属结构上，使得金属金属仅沉积在金属结构上。在帽金属上方形成第二电介质层。打开第二电介质层以形成端接在盖金属中的通孔。导电材料沉积在通孔中以通过盖金属提供与金属结构的接触。

56. 发明授权

US06210995B1 Method for manufacturing fusible links in a semiconductor device 失效
标题翻译：用于制造半导体器件中的可熔链节的方法
公开(公告)号：US06210995B1
公开(公告)日：2001-04-03
申请号：US09393096
申请日：1999-09-09
申请人： Axel C. Brintzinger , Jeffrey Gambino , Thomas Rupp , Scott Halle
发明人： Axel C. Brintzinger , Jeffrey Gambino , Thomas Rupp , Scott Halle
IPC分类号： H01L2182
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： In order to form a cavity for a fusible link in a semiconductor device, an etchable material is applied over and around a portion of the fusible link and the etchable material is coated with a protection layer. The access abutting the etchable material is formed through the protection layer. After the removal of the etchable material, the access is partially filled with a refilling material to thereby form the cavity.
摘要翻译：为了在半导体器件中形成用于可熔连接件的空腔，可蚀刻材料施加在可熔连接件的一部分上和周围，并且可蚀刻材料被涂覆有保护层。通过保护层形成邻接可蚀刻材料的通路。在去除可蚀刻材料之后，进入部分地填充有填充材料，从而形成空腔。

57. 发明授权

US07704804B2 Method of forming a crack stop laser fuse with fixed passivation layer coverage 有权
标题翻译：形成具有固定钝化层覆盖的裂纹停止激光熔丝的方法
公开(公告)号：US07704804B2
公开(公告)日：2010-04-27
申请号：US11953363
申请日：2007-12-10
申请人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
发明人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter
IPC分类号： H01L21/82
CPC分类号： H01L23/5258 , H01L23/585 , H01L24/02 , H01L24/03 , H01L24/12 , H01L2224/03 , H01L2224/0401 , H01L2224/05006 , H01L2224/05572 , H01L2224/13022 , H01L2224/16 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/05552
摘要： A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.
摘要翻译：在相邻熔丝结构之间的低k电介质或氧化硅层中形成裂纹阻挡空隙，用于在保险丝熔断操作期间防止相邻熔丝结构之间的裂纹传播。通过使用与形成互连结构同时形成的导电材料的蚀刻停止形状将钝化层固定就位。这产生了可靠且可重复的熔丝结构，其在容易制造的熔丝结构上具有可控钝化层。

58. 发明申请

US20080073742A1 STACKED IMAGE PACKAGE 有权
标题翻译：堆叠图像包
公开(公告)号：US20080073742A1
公开(公告)日：2008-03-27
申请号：US11943277
申请日：2007-11-20
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe , Robert Leidy , Stephen Luce , Richard Rassell , Edmund Sprogis
IPC分类号： H01L31/00 , H01L21/98
CPC分类号： H01L27/14618 , H01L25/0657 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/13091 , H01L2924/15151 , H01L2924/00014 , H01L2924/00
摘要： An imaging system for use in a digital camera or cell phone utilizes one chip for logic and one chip for image processing. The chips are interconnected using around-the-edge or through via conductors extending from bond pads on the active surface of the imaging chip to backside metallurgy on the imaging chip. The backside metallurgy of the imaging chip is connected to metallurgy on the active surface of the logic chip using an array of solder bumps in BGA fashion. The interconnection arrangement provides a CSP which matches the space constraints of a cell phone, for example. The arrangement also utilizes minimal wire lengths for reduced noise. Connection of the CSP to a carrier package may be either by conductive through vias or wire bonding. The CSP is such that the imaging chip may readily be mounted across an aperture in the wall of a cell phone, for example, so as to expose the light sensitive pixels on the active surface of said imaging chip to light.
摘要翻译：用于数码相机或手机的成像系统利用一个芯片用于逻辑和一个芯片用于图像处理。这些芯片使用围绕成像芯片的有源表面上的接合焊盘的边缘或通孔导体互连，从而在成像芯片上进行背面冶金。成像芯片的背面冶金采用BGA焊料凸块阵列与逻辑芯片的有源表面上的冶金连接。互连装置提供例如与手机的空间限制相匹配的CSP。该布置还利用最小的线长度来降低噪声。将CSP连接到载体封装可以通过通孔或引线键合导电。 CSP使得成像芯片可以容易地安装在例如手机的壁中的孔之间，以便将所述成像芯片的有效表面上的光敏像素曝光到光。

59. 发明申请

US20070262305A1 INTEGRATED CIRCUIT PROTECTION FROM ESD DAMAGE DURING FABRICATION 审中-公开
标题翻译：集成电路在制造过程中受到ESD损害的保护
公开(公告)号：US20070262305A1
公开(公告)日：2007-11-15
申请号：US11382492
申请日：2006-05-10
申请人： James Adkisson , Jeffrey Gambino , Richard Rassel , Steven Voldman
发明人： James Adkisson , Jeffrey Gambino , Richard Rassel , Steven Voldman
IPC分类号： H01L23/58
CPC分类号： H01L23/60 , H01L22/32 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit wafer containing a plurality of integrated circuit chips and having a common substrate, each chip formed with an internal region in the interior of the chip and a removable external region on the perimeter of the internal region and circuitry disposed preferably in the external region and connected to at least one pad of an integrated circuit chip and the wafer substrate to establish electrical connection during electrostatic discharge and prevent ESD damage. The pad and substrate are isolated during tested of the integrated circuit chips in the wafer. Preferably, the external region is removed when the integrated circuit chips are diced from the wafer.
摘要翻译：一种包含多个集成电路芯片并具有公共基板的半导体集成电路晶片，每个芯片在芯片的内部形成有内部区域，并且在内部区域的周边上具有可移除的外部区域，优选地设置在外部并且连接到集成电路芯片的至少一个焊盘和晶片衬底，以在静电放电期间建立电连接并防止ESD损坏。在晶片中的集成电路芯片的测试期间隔离衬垫和衬底。优选地，当从晶片切割集成电路芯片时，去除外部区域。

60. 发明申请

US20070200229A1 CHIP UNDERFILL IN FLIP-CHIP TECHNOLOGIES 有权
标题翻译：芯片技术中的芯片
公开(公告)号：US20070200229A1
公开(公告)日：2007-08-30
申请号：US11276380
申请日：2006-02-27
申请人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter , David Questad
发明人： Timothy Daubenspeck , Jeffrey Gambino , Christopher Muzzy , Wolfgang Sauter , David Questad
IPC分类号： H01L21/50 , H01L23/34
CPC分类号： H01L21/563 , H01L23/3128 , H01L24/10 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/29 , H01L24/81 , H01L2224/0401 , H01L2224/0603 , H01L2224/13 , H01L2224/13099 , H01L2224/14 , H01L2224/1403 , H01L2224/14051 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81194 , H01L2224/8121 , H01L2224/81815 , H01L2224/83194 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/00 , H01L2924/3512
摘要： A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.
摘要翻译：一种半导体结构及其形成方法。半导体结构包括（a）基板和（b）包括N个芯片焊球，N是正整数的芯片，并且N个芯片焊球与基板电接触。半导体结构还包括（c）分别在芯片的第一，第二，第三和第四角部处并夹在芯片和基板之间的第一，第二，第三和第四角底部填充区域。半导体结构还包括（d）夹在芯片和衬底之间的主要底部填充区域。第一，第二，第三和第四角底部填充区域，并且主底部填充区域基本上占据芯片和基板之间的整个空间。第一，第二，第三和第四角底部填充区域的角底层填充材料与主要底部填充区域的主要底部填充材料不同。

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