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51. 发明授权

US06791136B1 Memory device structure and method of fabricating the same 有权
标题翻译：存储器件结构及其制造方法
公开(公告)号：US06791136B1
公开(公告)日：2004-09-14
申请号：US10604366
申请日：2003-07-15
申请人： Hann-Jye Hsu , Chih-Wei Hung
发明人： Hann-Jye Hsu , Chih-Wei Hung
IPC分类号： H01L27108
CPC分类号： H01L27/11568 , H01L27/1052 , H01L27/115
摘要： A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a conductive gate layer. The silicon oxide layer is patterned during the same step of patterning the conductive layer, exposing the silicon nitride layer. Following that, a blanket dielectric layer is then formed on the substrate. This blanket dielectric layer is patterned with one etch step to form a spacer wall at the sides of the conductive gate layer.
摘要翻译：一种制造存储器件结构的方法，其中该方法包括形成隧道氧化物层，氮化硅层和氧化硅层的步骤。然后在氧化硅的顶部上形成导电层。然后将导电层图案化以形成导电栅极层。在图案化导电层的同一步骤中，氧化硅层被图案化，暴露氮化硅层。之后，在衬底上形成覆盖层的介电层。通过一个蚀刻步骤对该覆盖电介质层进行构图，以在导电栅极层的侧面形成间隔壁。

52. 发明授权

US08120956B2 Single-transistor EEPROM array and operation methods 有权
标题翻译：单晶体管EEPROM阵列及其操作方法
公开(公告)号：US08120956B2
公开(公告)日：2012-02-21
申请号：US12708725
申请日：2010-02-19
申请人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
发明人： Chun-Pei Wu , Chia-Ta Shieh , Chih-Wei Hung , Mars Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/0433 , H01L27/11565 , H01L27/11568
摘要： An integrated circuit structure includes an electrically erasable programmable read-only memory (EEPROM) array, which includes EEPROM cells arranged as rows and columns; a plurality of word-lines and a plurality of drain-lines extending in a column direction, and a plurality of source-lines extending in a row direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. Each of the plurality of drain-lines is connected to drains of the EEPROM cells in a same column, wherein none of the plurality of drain-lines are shared by neighboring columns of the EEPROM cells. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row.
摘要翻译：集成电路结构包括电可擦除可编程只读存储器（EEPROM）阵列，其包括排列成行和列的EEPROM单元; 沿列方向延伸的多条字线和多条漏极线以及沿行方向延伸的多条源极线。多个字线中的每一个连接到同一列中的EEPROM单元的控制栅极。多个漏极线中的每一个连接到同一列中的EEPROM单元的漏极，其中多个漏极线都不被EEPROM单元的相邻列共享。多个源极线中的每一个连接到同一行中的EEPROM单元的源极。

53. 发明申请

US20120025869A1 NON-VOLATILE FIELD PROGRAMMABLE GATE ARRAY 有权
标题翻译：非挥发性可编程门阵列
公开(公告)号：US20120025869A1
公开(公告)日：2012-02-02
申请号：US13209704
申请日：2011-08-15
申请人： Chih-Wei Hung , Chia-Ta Hsieh , Luan C. Tran
发明人： Chih-Wei Hung , Chia-Ta Hsieh , Luan C. Tran
IPC分类号： H03K19/177
CPC分类号： G11C16/10 , G11C16/0441 , H03K19/1776
摘要： A non-volatile memory device includes a first metal-oxide-semiconductor (CMOS) device coupled to a bit line and a word line and a second CMOS device coupled to the first CMOS device. The second CMOS device is also coupled to a complementary bit line and a complementary word line. The first and second CMOS devices are complementary to one another. An output node is coupled between the first CMOS device and the second CMOS device. A method of programming a non-volatile field programmable gate array (NV-FPGA) includes coupling an information handling system to the FPGA, performing a block erase of a plurality of memory cells in the FPGA, verifying that the block erase is successful, programming an upper page of the FPGA, verifying that the upper page programming is successful, programming a lower page of the FPGA and verifying that the lower page programming is successful.
摘要翻译：非易失性存储器件包括耦合到位线和字线的第一金属氧化物半导体（CMOS）器件和耦合到第一CMOS器件的第二CMOS器件。第二CMOS器件还耦合到互补位线和互补字线。第一和第二CMOS器件彼此互补。输出节点耦合在第一CMOS器件和第二CMOS器件之间。编程非易失性现场可编程门阵列（NV-FPGA）的方法包括将信息处理系统耦合到FPGA，对FPGA中的多个存储单元进行块擦除，验证块擦除成功，编程 FPGA的上一页，验证上页编程是否成功，编写FPGA的下一页，并验证下页编程是否成功。

54. 发明授权

US07580843B2 Synthesis subband filter process and apparatus 有权
标题翻译：合成子带滤波过程及装置
公开(公告)号：US07580843B2
公开(公告)日：2009-08-25
申请号：US11430702
申请日：2006-05-08
申请人： Chih-Hsien Chang , Chih-Wei Hung , Hsien-Ming Tsai
发明人： Chih-Hsien Chang , Chih-Wei Hung , Hsien-Ming Tsai
IPC分类号： G10L19/00 , G10L13/00 , G06F17/14
CPC分类号： G10L19/0208
摘要： A synthesis subband filter apparatus is provided. The apparatus is used for processing 18 sets of signals which each includes 32 subband sampling signals in accordance with a specification providing 512 window coefficients. The apparatus includes a processor for processing the 18 sets of signals in sequence. The processor further includes a converting module and a generating module. The converting module is used for converting the 32 subband sampling signals of the set of signals being processed into 32 converted vectors by use of 32-points discrete cosine transform (DCT), and writing the 32 converted vectors into 512 default vectors with a first-in, first-out queue. The generating module is used for generating 32 pulse code modulation (PCM) signals, relative to the set of signals being processed according to a set of synthesis formulae proposed in this invention.
摘要翻译：提供合成子带滤波器装置。该装置用于处理根据提供512个窗系数的规范的18组信号，每组信号包括32个子带采样信号。该装置包括用于依次处理18组信号的处理器。处理器还包括转换模块和生成模块。转换模块用于通过使用32点离散余弦变换（DCT）将被处理的信号组的32个子带采样信号转换为32个转换的矢量，并将32个转换的矢量写入512个默认矢量，在，先出队列。生成模块用于产生32个脉码调制（PCM）信号，相对于根据本发明中提出的一组合成公式处理的信号集合。

55. 发明申请

US20090109762A1 METHOD FOR PROGRAMMING NON-VOLATILE MEMORY 审中-公开
标题翻译：编程非易失性存储器的方法
公开(公告)号：US20090109762A1
公开(公告)日：2009-04-30
申请号：US11930164
申请日：2007-10-31
申请人： Chen-Hao Huang , Chih-Wei Hung , Chih-Yuan Chen
发明人： Chen-Hao Huang , Chih-Wei Hung , Chih-Yuan Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： A method for programming non-volatile memory utilizes substrate hot carrier effect to conduct programming operations. A forward bias voltage is applied between an N-type well region and a P-type well region so as to inject electrons in the N-type well region into the P-type well region. After that, the electrons are accelerated by a depletion region established by a voltage applied to a source region and a drain region, and a vertical electrical field established between a control gate and the P-type well region further forces the electrons to be injected into a charge storage layer. Since the present invention adopts the substrate hot carrier effect to inject carriers into the charge storage layer, the required program operation voltage is low, which benefits to save power consumption and enhance the reliability of the device.
摘要翻译：用于编程非易失性存储器的方法利用衬底热载体效应来进行编程操作。在N型阱区域和P型阱区域之间施加正向偏置电压，以将N型阱区域中的电子注入到P型阱区域中。之后，电子被施加到源极区域和漏极区域的电压建立的耗尽区域加速，并且在控制栅极与P型阱区域之间建立的垂直电场进一步迫使电子注入电荷存储层。由于本发明采用基板热载流子效应将载流子注入电荷存储层，因此所需的编程操作电压低，有利于节省功耗并提高器件的可靠性。

56. 发明申请

US20080143998A1 METHOD FOR ELIMINATING INTERNAL REFLECTION OF RANGE FINDING SYSTEM AND RANGE FINDING SYSTEM APPLYING THE SAME 失效
标题翻译：消除范围内发现系统的内部反射方法和应用其范围的发现系统
公开(公告)号：US20080143998A1
公开(公告)日：2008-06-19
申请号：US12037857
申请日：2008-02-26
申请人： Chih-Wei Hung
发明人： Chih-Wei Hung
IPC分类号： G01C3/00
CPC分类号： G01S7/4812 , G01S7/497 , G02B7/32
摘要： A method for eliminating internal reflection signal in a range finding system is disclosed, including the steps of receiving a range-finding signal reflected by an object and an internal reflection signal caused by internal reflection of the range finding system, converting the range finding signal and internal reflection signal, as a combination, into an electrical current signal, cropping the electrical current signal in a time interval for the electrical current signal to pass so as to generate a first electrical signal indicating the internal reflection signal, and subtracting the first electrical signal from the current signal to provide a second electrical signal representing the range-finding signal reflected by the object.
摘要翻译：公开了一种用于消除测距系统中的内反射信号的方法，包括以下步骤：接收由对象反射的测距信号和由测距系统的内部反射引起的内部反射信号，转换测距信号和作为组合的内部反射信号作为电流信号，在电流信号通过的时间间隔内修剪电流信号，以产生指示内部反射信号的第一电信号，并且减去第一电信号从当前信号提供表示由对象反射的测距信号的第二电信号。

57. 发明授权

US06870212B2 Trench flash memory device and method of fabricating thereof 有权
标题翻译：沟槽式闪存装置及其制造方法
公开(公告)号：US06870212B2
公开(公告)日：2005-03-22
申请号：US10065345
申请日：2002-10-07
申请人： Ko-Hsing Chang , Chih-Wei Hung
发明人： Ko-Hsing Chang , Chih-Wei Hung
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/76
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/11556
摘要： A method of fabricating a trench flash memory device, where the method includes forming a patterned mask layer on the substrate and using it as the mask for form a trench in the substrate. Next, a source region is formed in the substrate near the bottom of the trench, followed by forming a tunnel oxide layer, a floating gate, a gate dielectric layer and a control in the trench. After removing the mask layer to expose the substrate, a drain region is further formed in the substrate. In this invention, since the trench flash memory device has a cylindrical shape with the tunnel oxide layer, the floating gate and the gate dielectric layer wrapping around the control gate, the overlap area between the floating gate and the control gate is increased, resulting in a higher gate coupling rate (GCR), a lower required operation voltage and a higher device operation speed and efficiency.
摘要翻译：一种制造沟槽闪速存储器件的方法，其中所述方法包括在衬底上形成图案化掩模层并将其用作在衬底中形成沟槽的掩模。接下来，在沟槽的底部附近的衬底中形成源极区，然后在沟槽中形成隧道氧化物层，浮栅，栅极电介质层和控制。在去除掩模层以露出衬底之后，在衬底中进一步形成漏区。在本发明中，由于沟槽式闪速存储器件具有隧道氧化层的圆柱形状，浮动栅极和围绕控制栅极的栅介质层，所以浮栅和控制栅之间的重叠面积增加，导致更高的栅极耦合速率（GCR），较低的所需工作电压和更高的器件操作速度和效率。

58. 发明授权

US06834011B2 Structure, fabrication method and operating method for flash memory 有权
标题翻译：闪存的结构，制作方法和操作方法
公开(公告)号：US06834011B2
公开(公告)日：2004-12-21
申请号：US10829414
申请日：2004-04-20
申请人： Chih-Wei Hung , Da Sung
发明人： Chih-Wei Hung , Da Sung
IPC分类号： G11C1600
CPC分类号： G11C16/0416 , G11C16/14
摘要： A flash memory structure. The structure includes device isolation regions defined on an active area of a substrate, a deep well of first conductive type, stacked gate structures, a tunneling oxide layer, wells of second conductive type, sources and drains, wherein the aforementioned deep well of first conductive type is located in the active area and below the device isolation regions. The aforementioned wells of second conductive type are formed in the area corresponding to the drains and below the device isolation regions between the adjacent stacked gate structures. The aforementioned sources and drains are in the active areas located on both sides of the control gates, wherein the drains are enclosed by the wells of second conductive type; and the sources are located on both sides of the wells of second conductive type and electrically connected with each other via the deep well of first conductive type. Moreover, the present invention also provides a fabrication method and an operating method for the aforementioned structure.
摘要翻译：闪存结构。该结构包括限定在衬底的有源区域上的器件隔离区域，第一导电类型的深阱，堆叠栅极结构，隧道氧化物层，第二导电类型的阱，源极和漏极，其中上述第一导电深阱类型位于设备隔离区域的有效区域和下方。第二导电类型的上述阱形成在相应于排水沟的区域中，并在相邻堆叠的栅极结构之间的器件隔离区的下面。上述源极和漏极位于控制栅极两侧的有源区域中，其中漏极由第二导电类型的阱包围; 并且源位于第二导电类型的阱的两侧，并经由第一导电类型的深阱彼此电连接。此外，本发明还提供了上述结构的制造方法和操作方法。

59. 发明授权

US06778438B2 Structure, fabrication method and operating method for flash memory 有权
公开(公告)号：US06778438B2
公开(公告)日：2004-08-17
申请号：US10269460
申请日：2002-10-11
申请人： Chih-Wei Hung , Da Sung
发明人： Chih-Wei Hung , Da Sung
IPC分类号： G11C1600
CPC分类号： G11C16/0416 , G11C16/14
摘要： A flash memory structure. The structure includes device isolation regions defined on an active area of a substrate, a deep well of first conductive type, stacked gate structures, a tunneling oxide layer, wells of second conductive type, sources and drains, wherein the aforementioned deep well of first conductive type is located in the active area and below the device isolation regions. The aforementioned wells of second conductive type are formed in the area corresponding to the drains and below the device isolation regions between the adjacent stacked gate structures. The aforementioned sources and drains are in the active areas located on both sides of the control gates, wherein the drains are enclosed by the wells of second conductive type; and the sources are located on both sides of the wells of second conductive type and electrically connected with each other via the deep well of first conductive type. Moreover, the present invention also provides a fabrication method and an operating method for the aforementioned structure.

60. 发明授权

US06757208B1 Dual-bit nitride read only memory cell with parasitic amplifier and methods of fabricating and reading the same 有权
标题翻译：具有寄生放大器的双位氮化物只读存储单元及其制造和读取方法
公开(公告)号：US06757208B1
公开(公告)日：2004-06-29
申请号：US10665599
申请日：2003-09-22
申请人： Chiu-Tsung Huang , Chih-Wei Hung
发明人： Chiu-Tsung Huang , Chih-Wei Hung
IPC分类号： G11C1714
CPC分类号： G11C16/0475
摘要： Dual-bit nitride read only memory (NROM) cell with parasitic amplifier and method of fabricating and reading the same. A NROM cell comprises a semiconductor substrate with a first well region having a conductive type opposite that of the substrate disposed therein. A second well region having a conductive type opposite to the first well region is disposed in the first well region. A gate dielectric layer is disposed over portions of the second well region, wherein the gate dielectric layer comprises a nitride layer. A conductive layer is disposed on the gate dielectric layer to form a gate. And, a pair of first doped regions having a conductive type opposite to the second well region are symmetrically disposed in the second well region of both sides of the gate, wherein one of the first doped regions, the second well region and the first well region constitute a parasitic current amplifier.
摘要翻译：具有寄生放大器的双位氮化物只读存储器（NROM）单元及其制造和读取方法。 NROM单元包括半导体衬底，其具有与设置在其中的衬底的导电类型相反的导电类型的第一阱区。具有与第一阱区相对的导电类型的第二阱区设置在第一阱区中。栅介质层设置在第二阱区的部分上，其中栅介质层包括氮化物层。导电层设置在栅介质层上以形成栅极。并且，具有与第二阱区域相反的导电类型的一对第一掺杂区域对称地设置在栅极两侧的第二阱区域中，其中第一掺杂区域，第二阱区域和第一阱区域中的一个构成寄生电流放大器。

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