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51. 发明授权

US08460508B2 Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device 有权
标题翻译：同步脉冲等离子体蚀刻设备及制造半导体器件的方法
公开(公告)号：US08460508B2
公开(公告)日：2013-06-11
申请号：US12591602
申请日：2009-11-24
申请人： Ken Tokashiki , Hong Cho , Jeong-Dong Choe
发明人： Ken Tokashiki , Hong Cho , Jeong-Dong Choe
IPC分类号： H01L21/3065 , H01L21/302 , C23C16/00 , C23C16/50 , C23C16/52
CPC分类号： H01J37/32165 , H01J37/32082 , H01J37/32174
摘要： Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.
摘要翻译：同步脉冲等离子体蚀刻设备包括第一电极和被配置为在等离子体蚀刻室中产生等离子体的一个或多个第二电极。第一射频功率输出单元被配置为向第一电极施加具有第一频率和第一占空比的第一射频功率，并且输出包括关于第一射频功率的相位的信息的控制信号。至少一个第二射频功率输出单元被配置为将具有第二频率和第二占空比的第二射频功率应用于第二电极中的对应的第二电极。第二射频功率输出单元被配置为响应于控制信号控制与第一射频功率同步的第二射频功率或者与第一射频功率相位差。

52. 发明授权

US08059469B2 Semiconductor device including driving transistors 有权
标题翻译：包括驱动晶体管的半导体器件
公开(公告)号：US08059469B2
公开(公告)日：2011-11-15
申请号：US12481916
申请日：2009-06-10
申请人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
发明人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
IPC分类号： G11C11/34
CPC分类号： H01L27/11573 , H01L21/823425 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L29/78
摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.
摘要翻译：半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

53. 发明申请

US20090230456A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090230456A1
公开(公告)日：2009-09-17
申请号：US12382232
申请日：2009-03-11
申请人： Young-Bae Yoon , Jeong-Dong Choe , Dong-Hoon Jang , Ki-Hyun Kim
发明人： Young-Bae Yoon , Jeong-Dong Choe , Dong-Hoon Jang , Ki-Hyun Kim
IPC分类号： H01L29/788 , H01L27/06
CPC分类号： H01L21/823481 , H01L21/823456 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.
摘要翻译：半导体器件包括具有第一区域和第二区域的衬底，第一区域中的第一晶体管，第二区域中的第二晶体管，第一区域和第二区域之间的隔离层，以及至少一个掩埋屏蔽结构在隔离层上。

54. 发明申请

US20110156125A1 NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS 有权
标题翻译：非挥发性半导体器件，包括浮动门和相关系统
公开(公告)号：US20110156125A1
公开(公告)日：2011-06-30
申请号：US13040380
申请日：2011-03-04
申请人： Se-Hoon LEE , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon LEE , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

55. 发明授权

US06271108B1 Method of forming a contact in semiconductor device 有权
标题翻译：在半导体器件中形成接触的方法
公开(公告)号：US06271108B1
公开(公告)日：2001-08-07
申请号：US09313258
申请日：1999-05-18
申请人： Jeong-Dong Choe
发明人： Jeong-Dong Choe
IPC分类号： H01L2144
CPC分类号： H01L21/76897
摘要： The present invention relates to a method of forming a contact in semiconductor device, more particularly, to a method of forming a borderless contact in semiconductor device which minimizes loss of field oxide on forming a contact hole, reducing leakage current at an interface between an active area and a field area and preventing another loss of silicon and silicide in the active area by forming a barrier layer on a field oxide layer for separating devices in order to enhance a process margin of forming the contact hole in the active area due to a reduced design rule and an increased device integrity. The present invention includes the steps of forming a trench on a semiconductor substrate wherein the trench defines an active area and a field area, filling up the trench with an insulating layer, forming a barrier layer just on the insulating layer, forming a transistor in the active layer wherein the transistor has an impurity diffusion region, forming an insulating interlayer on a surface of the substrate including the transistor and the barrier layer, and forming at least a contact hole by removing a predetermined portion of the insulating interlayer wherein the contact hole exposes both a portion of the impurity diffusion region and another portion of the barrier layer.
摘要翻译：本发明涉及一种在半导体器件中形成接触的方法，更具体地说，涉及一种在半导体器件中形成无边界接触的方法，该方法使形成接触孔的场氧化物的损耗最小化，减少了在活性物质之间的界面处的泄漏电流区域和场区，并通过在用于分离器件的场氧化物层上形成阻挡层来防止有源区中的硅和硅化物的另一损失，以便增强由于减少了在有源区中形成接触孔的工艺余量设计规则和增加的设备完整性。本发明包括在半导体衬底上形成沟槽的步骤，其中沟槽限定有源区和场区，用绝缘层填充沟槽，在绝缘层上形成阻挡层，在绝缘层上形成晶体管活性层，其中所述晶体管具有杂质扩散区，在包括所述晶体管和所述阻挡层的所述衬底的表面上形成绝缘中间层，并且通过去除所述绝缘中间层的预定部分形成至少接触孔，其中所述接触孔暴露杂质扩散区域的一部分和势垒层的另一部分。

56. 发明授权

US07902024B2 Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems 失效
标题翻译：包括浮动栅极的非易失性半导体器件，其制造方法和相关系统
公开(公告)号：US07902024B2
公开(公告)日：2011-03-08
申请号：US11896982
申请日：2007-09-07
申请人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

57. 发明申请

US20100173469A1 METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES 有权
标题翻译：制造电荷陷波型非易失性存储器件的方法
公开(公告)号：US20100173469A1
公开(公告)日：2010-07-08
申请号：US12651781
申请日：2010-01-04
申请人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
发明人： Hak-Sun Lee , Kyoung-Sub Shin , Jeong-Dong Choe
IPC分类号： H01L21/76
CPC分类号： H01L27/11568
摘要： Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.
摘要翻译：一些方法涉及制造电荷陷阱型非易失性存储器件。可以形成在衬底中沿第一方向延伸的隔离层图案。通过使邻近隔离层图案的基板的暴露表面凹陷而在基板中形成凹部单元。隧道绝缘层和电荷陷阱层依次形成在基板上。图案化隧道绝缘层和电荷陷阱层，通过蚀刻衬底的限定区域，隔离层图案，隧道绝缘层，隔离层状图案，隔离层状图案，隧道绝缘层，并且电荷陷阱层直到设置在凹陷单元的底表面上的电荷陷阱层的顶表面与隔离层图案的顶表面对准。形成了覆盖电荷陷阱层图案，隔离层图案和插入在电荷阱图案之间的基板的限定区域的阻挡绝缘层。在阻挡绝缘层上形成面对电荷陷阱层图案的栅电极图案。该制造过程可以减小单元存储单元之间的电荷扩展和/或可以防止/避免阻塞绝缘层的击穿电压的降低。

58. 发明授权

US08330205B2 Nonvolatile semiconductor device including a floating gate and associated systems 有权
标题翻译：包括浮动栅极和相关系统的非易失性半导体器件
公开(公告)号：US08330205B2
公开(公告)日：2012-12-11
申请号：US13040380
申请日：2011-03-04
申请人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

59. 发明授权

US08039905B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08039905B2
公开(公告)日：2011-10-18
申请号：US12382232
申请日：2009-03-11
申请人： Young-Bae Yoon , Jeong-Dong Choe , Dong-Hoon Jang , Ki-Hyun Kim
发明人： Young-Bae Yoon , Jeong-Dong Choe , Dong-Hoon Jang , Ki-Hyun Kim
IPC分类号： H01L29/66
CPC分类号： H01L21/823481 , H01L21/823456 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.
摘要翻译：半导体器件包括具有第一区域和第二区域的衬底，第一区域中的第一晶体管，第二区域中的第二晶体管，第一区域和第二区域之间的隔离层，以及至少一个掩埋屏蔽结构在隔离层上。

60. 发明申请

US20100130018A1 Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device 有权
标题翻译：同步脉冲等离子体蚀刻设备及制造半导体器件的方法
公开(公告)号：US20100130018A1
公开(公告)日：2010-05-27
申请号：US12591602
申请日：2009-11-24
申请人： Ken Tokashiki , Hong Cho , Jeong-Dong Choe
发明人： Ken Tokashiki , Hong Cho , Jeong-Dong Choe
IPC分类号： H01L21/3065
CPC分类号： H01J37/32165 , H01J37/32082 , H01J37/32174
摘要： Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.
摘要翻译：同步脉冲等离子体蚀刻设备包括第一电极和被配置为在等离子体蚀刻室中产生等离子体的一个或多个第二电极。第一射频功率输出单元被配置为向第一电极施加具有第一频率和第一占空比的第一射频功率，并且输出包括关于第一射频功率的相位的信息的控制信号。至少一个第二射频功率输出单元被配置为将具有第二频率和第二占空比的第二射频功率应用于第二电极中的对应的第二电极。第二射频功率输出单元被配置为响应于控制信号控制与第一射频功率同步的第二射频功率或者与第一射频功率相位差。

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