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1. 发明授权

US07902024B2 Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems 失效
标题翻译：包括浮动栅极的非易失性半导体器件，其制造方法和相关系统
公开(公告)号：US07902024B2
公开(公告)日：2011-03-08
申请号：US11896982
申请日：2007-09-07
申请人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

2. 发明申请

US20110156125A1 NONVOLATILE SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE AND ASSOCIATED SYSTEMS 有权
标题翻译：非挥发性半导体器件，包括浮动门和相关系统
公开(公告)号：US20110156125A1
公开(公告)日：2011-06-30
申请号：US13040380
申请日：2011-03-04
申请人： Se-Hoon LEE , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon LEE , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

3. 发明申请

US20080265304A1 Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems 失效
标题翻译：包括浮动栅极的非易失性半导体器件，其制造方法和相关系统
公开(公告)号：US20080265304A1
公开(公告)日：2008-10-30
申请号：US11896982
申请日：2007-09-07
申请人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

4. 发明授权

US08330205B2 Nonvolatile semiconductor device including a floating gate and associated systems 有权
标题翻译：包括浮动栅极和相关系统的非易失性半导体器件
公开(公告)号：US08330205B2
公开(公告)日：2012-12-11
申请号：US13040380
申请日：2011-03-04
申请人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
发明人： Se-Hoon Lee , Donghoon Jang , Jong Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.
摘要翻译：存储器件包括在衬底中相邻隔离层之间的衬底上的第一浮置栅电极，第一浮置栅极的至少一部分突出在相邻隔离层的一部分上方，第二浮栅电极电连接到第一浮栅浮栅电极，在至少一个相邻的隔离层上，第一和第二浮置栅电极之上的电介质层，以及介电层上的控制栅极以及第一和第二浮栅电极。

5. 发明授权

US08059469B2 Semiconductor device including driving transistors 有权
标题翻译：包括驱动晶体管的半导体器件
公开(公告)号：US08059469B2
公开(公告)日：2011-11-15
申请号：US12481916
申请日：2009-06-10
申请人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
发明人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
IPC分类号： G11C11/34
CPC分类号： H01L27/11573 , H01L21/823425 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L29/78
摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.
摘要翻译：半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

6. 发明申请

US20100008152A1 SEMICONDUCTOR DEVICE INCLUDING DRIVING TRANSISTORS 有权
标题翻译：包括驱动晶体管的半导体器件
公开(公告)号：US20100008152A1
公开(公告)日：2010-01-14
申请号：US12481916
申请日：2009-06-10
申请人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
发明人： Se-Hoon Lee , Choong-Ho Lee , Jeong-Dong Choe , Tae-Yong Kim , Woo-Jung Kim , Dong-Hoon Jang , Young-Bae Yoon , Ki-Hyun Kim , Min-Tai Yu
IPC分类号： G11C11/4096 , G11C5/06
CPC分类号： H01L27/11573 , H01L21/823425 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531 , H01L27/11568 , H01L29/78
摘要： A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.
摘要翻译：半导体器件包括限定在衬底中的驱动有源区和设置在驱动有源区的至少三个驱动晶体管。驱动晶体管共享一个共同的源极/漏极，并且每个驱动晶体管包括彼此独立的各个源极/漏极。公共源极/漏极和各个源极/漏极设置在驱动有源区域中。

7. 发明授权

US08049269B2 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08049269B2
公开(公告)日：2011-11-01
申请号：US11898266
申请日：2007-09-11
申请人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
发明人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
IPC分类号： H01L29/792 , H01L29/788 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.
摘要翻译：在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上垂直于第一方向。因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

8. 发明申请

US20080061361A1 Non-volatile memory device and method of manufacturing the same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20080061361A1
公开(公告)日：2008-03-13
申请号：US11898266
申请日：2007-09-11
申请人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
发明人： Se-Hoon Lee , Kyu-Charn Park , Jeong-Dong Choe
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.
摘要翻译：在非易失性存储器件中，可以在衬底上形成沿第一方向延伸的活性鳍结构。隧道绝缘层可以形成在活动鳍结构和沟槽底表面的表面上，沟槽绝缘层可以由活性鳍结构限定。电荷俘获层和阻挡层可以顺序形成在隧道绝缘层上。栅极电极结构可以包括设置在有源鳍结构的顶表面上的第一部分和与可以设置在沟槽的底表面之上的电荷俘获层的部分垂直间隔开的第二部分，并且可以在基本上垂直于第一方向。因此，电荷捕捉层中的横向电子扩散可能减少，从而可以提高非易失性存储器件的数据保持性能和/或可靠性。

9. 发明申请

US20080001209A1 Non-volatile memory device and method of manufacturing the non-volatile memory device 审中-公开
标题翻译：非易失性存储器件和制造非易失性存储器件的方法
公开(公告)号：US20080001209A1
公开(公告)日：2008-01-03
申请号：US11783548
申请日：2007-04-10
申请人： Eun-Suk Cho , Kyu-Charn Park , Jong-Jin Lee , Jeong-Dong Choe
发明人： Eun-Suk Cho , Kyu-Charn Park , Jong-Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42336
摘要： A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.
摘要翻译：非易失性存储器件可以包括具有场区域和包括圆形上边缘部分和平坦上中心部分的有源区域的基板，在有源区域的平坦上中心部分上的有效隧道氧化物层，分裂浮动栅极电极在有效隧道氧化物层上，浮栅电极的宽度大于有效隧道氧化物层的宽度，浮栅电极上的电介质层图案，包括金属氧化物的电介质层图案和控制栅电极在电介质层图案上。

10. 发明申请

US20070205459A1 Nonvolatile memory devices and methods of forming the same 审中-公开
标题翻译：非易失存储器件及其形成方法
公开(公告)号：US20070205459A1
公开(公告)日：2007-09-06
申请号：US11653359
申请日：2007-01-16
申请人： Eun-Suk Cho , Dong-Gun Park , Choong-Ho Lee , Jong-Jin Lee , Jeong-Dong Choe
发明人： Eun-Suk Cho , Dong-Gun Park , Choong-Ho Lee , Jong-Jin Lee , Jeong-Dong Choe
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833 , H01L29/7854 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a semiconductor pin including a first semiconductor pattern, a second semiconductor pattern on the first semiconductor pattern, and a third semiconductor pattern, disposed between the first semiconductor pattern and the second semiconductor pattern, connecting the first semiconductor pattern and the second semiconductor pattern, a charge storage layer on the second semiconductor pattern with a tunneling insulation layer interposed therebetween, and a gate electrode on the charge storage layer with a blocking insulation layer interposed therebetween, wherein a width of the second semiconductor pattern is greater than a width of the third semiconductor pattern.
摘要翻译：非易失性存储器件包括：半导体引脚，包括第一半导体图案，第一半导体图案上的第二半导体图案和设置在第一半导体图案和第二半导体图案之间的第三半导体图案，将第一半导体图案和第二半导体图案半导体图案，在第二半导体图案上的电荷存储层，其间插入有隧道绝缘层，以及在电荷存储层上的栅电极，其间插入有阻挡绝缘层，其中第二半导体图案的宽度大于宽度的第三半导体图案。

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