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51. 发明申请

US20080142873A1 INTEGRATED CIRCUIT SYSTEM WITH METAL AND SEMI-CONDUCTING GATE 有权
标题翻译：具有金属和半导体门的集成电路系统
公开(公告)号：US20080142873A1
公开(公告)日：2008-06-19
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

52. 发明授权

US07265014B1 Avoiding field oxide gouging in shallow trench isolation (STI) regions 有权
标题翻译：在浅沟槽隔离（STI）区域避免场氧化物气刨
公开(公告)号：US07265014B1
公开(公告)日：2007-09-04
申请号：US10799413
申请日：2004-03-12
申请人： Angela T. Hui , Jusuke Ogura , Yider Wu
发明人： Angela T. Hui , Jusuke Ogura , Yider Wu
IPC分类号： H01L21/764 , H01L29/00
CPC分类号： H01L21/76224
摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.
摘要翻译：一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。可以在STI区域中蚀刻沟槽并填充绝缘材料。抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。可以将保护盖回蚀以暴露ARC层。然而，保护盖仍然覆盖并保护绝缘材料。通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

53. 发明授权

US07238571B1 Non-volatile memory device with increased reliability 有权
标题翻译：非易失性存储器件具有更高的可靠性
公开(公告)号：US07238571B1
公开(公告)日：2007-07-03
申请号：US11063560
申请日：2005-02-24
申请人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
发明人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.
摘要翻译：存储器件可以包括多个存储器单元，形成在存储器单元上的第一层间电介质和形成在层间电介质上的至少一个金属层。介电层可以形成在金属层的上方。电介质层可以表示在存储器件的上表面处或附近形成的覆盖层，并且可以在相对低的温度下沉积。

54. 发明授权

US06803267B1 Silicon containing material for patterning polymeric memory element 有权
标题翻译：含硅材料用于图案化聚合物记忆元件
公开(公告)号：US06803267B1
公开(公告)日：2004-10-12
申请号：US10614484
申请日：2003-07-07
申请人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
发明人： Ramkumar Subramanian , Christopher F. Lyons , Matthew S. Buynoski , Patrick K. Cheung , Angela T. Hui , Ashok M. Khathuria , Sergey D. Lopatin , Minh Van Ngo , Jane V. Oglesby , Terence C. Tong , James J. Xie
IPC分类号： H01L21336
CPC分类号： H01L27/28 , B82Y10/00 , G11C13/0014 , G11C13/0016 , H01L51/0018
摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.
摘要翻译：本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料上电极通过有机半导体材料和被动材料到下电极。有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。

55. 发明授权

US06753247B1 Method(s) facilitating formation of memory cell(s) and patterned conductive 失效
标题翻译：促进形成记忆体和图案化的导电聚合物膜的方法
公开(公告)号：US06753247B1
公开(公告)日：2004-06-22
申请号：US10285183
申请日：2002-10-31
申请人： Uzodinma Okoroanyanwu , Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Mark S. Chang , Ramkumar Subramanian , Angela T. Hui
发明人： Uzodinma Okoroanyanwu , Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Mark S. Chang , Ramkumar Subramanian , Angela T. Hui
IPC分类号： H01L214763
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/285
摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.
摘要翻译：公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线电介质材料，使得顶部电极通过通孔连接到字线。

56. 发明授权

US06171919B2 MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation 有权
标题翻译： MOS晶体管形成工艺包括用于改善硅化物形成的后间隔蚀刻表面处理
公开(公告)号：US06171919B2
公开(公告)日：2001-01-09
申请号：US09361155
申请日：1999-07-27
申请人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
发明人： Paul R. Besser , Minh Van Ngo , Simon S. Chan , Angela T. Hui
IPC分类号： H01L21336
CPC分类号： H01L29/665
摘要： Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include removing carbonaceous residues by performing a hydrogen ion plasma treatment.
摘要翻译：通过自对准硅化物工艺形成具有减小的或最小的结泄漏的亚微米尺寸的超浅结MOS和/或CMOS晶体管器件，其中在自对准硅化物处理之前除去由用于侧壁间隔物形成的反应等离子体蚀刻而导致的硅衬底表面上的碳质残渣。实施例包括通过进行氢离子等离子体处理来除去碳质残渣。

57. 发明授权

US6124201A Method for manufacturing semiconductors with self-aligning vias 失效
标题翻译：具有自对准通孔的半导体制造方法
公开(公告)号：US6124201A
公开(公告)日：2000-09-26
申请号：US097126
申请日：1998-06-12
申请人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
发明人： Fei Wang , Robin Cheung , Mark S. Chang , Richard J. Huang , Angela T. Hui
IPC分类号： H01L21/60 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76802
摘要： An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. He stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.
摘要翻译：具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。他停止氮化物层是以矩形通孔结构蚀刻氮化物，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

58. 发明授权

US08367493B1 Void free interlayer dielectric 有权
标题翻译：无空隙层间电介质
公开(公告)号：US08367493B1
公开(公告)日：2013-02-05
申请号：US11109719
申请日：2005-04-20
申请人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
发明人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
IPC分类号： H01L21/8238
CPC分类号： H01L23/291 , H01L21/823425 , H01L21/823475 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
摘要翻译：一种制造非易失性存储器件的方法包括形成多个存储单元。该方法还包括在存储器单元上沉积第一介电层，其中第一介电层是具有基本均匀厚度的共形层。该方法还包括在第一介电层上沉积第二电介质层。第一和第二电介质层一起形成没有空隙的层间电介质。

59. 发明授权

US08283718B2 Integrated circuit system with metal and semi-conducting gate 有权
标题翻译：具有金属和半导体栅极的集成电路系统
公开(公告)号：US08283718B2
公开(公告)日：2012-10-09
申请号：US11611856
申请日：2006-12-16
申请人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
发明人： Angela T. Hui , Mark S. Chang , Kuo-Tung Chang , Scott A. Bell
IPC分类号： H01L29/792
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for forming an integrated circuit system is provided including forming a semi-conducting layer over a substrate, forming a spacer stack having a gap filler adjacent to the semi-conducting layer and a inter-layer dielectric over the gap filler, forming a transition layer having a recess over the semi-conducting layer and adjacent to the spacer stack, and forming a metal layer in the recess.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括在衬底上形成半导电层，形成间隔层叠层，其间隔填充物与半导体层相邻，间隙填料上形成层间电介质，形成过渡层该层在半导体层上具有凹陷并且与间隔物堆叠相邻，并且在凹部中形成金属层。

60. 发明申请

US20120032308A1 GATE TRIM PROCESS USING EITHER WET ETCH OR DRY ETCH APPROACH TO TARGET CD FOR SELECTED TRANSISTORS 有权
标题翻译：使用蚀刻或干蚀刻方法对选定的晶体管的目标光盘进行栅格扫描过程
公开(公告)号：US20120032308A1
公开(公告)日：2012-02-09
申请号：US13278343
申请日：2011-10-21
申请人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
发明人： Bradley M. Davis , Jihwan Choi , Angela T. Hui
IPC分类号： H01L21/306 , H01L29/06
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132 , H01L21/823456
摘要： Disclosed are methods and devices for targeting CD of selected transistors in a semiconductor device. Varying CD is done by forming hard mask lines in a hard mask layer that have varying amounts of spacer material associated therewith. Hard mask lines corresponding to selected transistors are either left covered or uncovered by a resist applied over the hard mask layer. Then, spacer material is selectively removed from the hard mask lines to vary the width of hard mask lines and associated side wall spacers. A gate layer is then etched through the spaces in the hard mask lines to form gate lines having varying widths and targeted CD.
摘要翻译：公开了用于在半导体器件中靶向所选晶体管的CD的方法和装置。通过在硬掩模层中形成具有不同量的与其相关联的间隔物材料的硬掩模线来完成不同的CD。对应于所选择的晶体管的硬掩模线被被涂覆在硬掩模层上的抗蚀剂覆盖或未覆盖。然后，从硬掩模线选择性地去除间隔物材料以改变硬掩模线和相关联的侧壁间隔物的宽度。然后通过硬掩模线中的空间蚀刻栅极层以形成具有不同宽度的栅极线和目标CD。

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