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1. 发明授权

US07265014B1 Avoiding field oxide gouging in shallow trench isolation (STI) regions 有权
标题翻译：在浅沟槽隔离（STI）区域避免场氧化物气刨
公开(公告)号：US07265014B1
公开(公告)日：2007-09-04
申请号：US10799413
申请日：2004-03-12
申请人： Angela T. Hui , Jusuke Ogura , Yider Wu
发明人： Angela T. Hui , Jusuke Ogura , Yider Wu
IPC分类号： H01L21/764 , H01L29/00
CPC分类号： H01L21/76224
摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.
摘要翻译：一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。可以在STI区域中蚀刻沟槽并填充绝缘材料。抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。可以将保护盖回蚀以暴露ARC层。然而，保护盖仍然覆盖并保护绝缘材料。通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

2. 发明授权

US06479411B1 Method for forming high quality multiple thickness oxide using high temperature descum 失效
标题翻译：使用高温除垢法形成高品质多层氧化物的方法
公开(公告)号：US06479411B1
公开(公告)日：2002-11-12
申请号：US09532347
申请日：2000-03-21
申请人： Angela T. Hui , Jusuke Ogura
发明人： Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21311
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31111 , H01L21/31116 , H01L21/31138 , H01L21/31662 , Y10S438/906 , Y10S438/942 , Y10S438/948
摘要： A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least one region of the oxide layer. The substrate is then heated and descummed to remove any residue resulting from developing the photoresist. Alternatively, the photoresist layer may be cured prior to heating and descumming the substrate. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.
摘要翻译：一种用于通过消除除去所引起的缺陷来形成具有不同厚度的高质量多层氧化物层的方法。该方法包括形成氧化物层，用光致抗蚀剂层掩蔽氧化物层，以及显影光致抗蚀剂层以暴露氧化物层的至少一个区域。然后将基材加热除去以除去由显影光致抗蚀剂产生的残留物。或者，光致抗蚀剂层可以在加热和除去基板之前固化。然后蚀刻氧化物层，并且在衬底上生长另一层氧化物之前剥离剩余的光致抗蚀剂。

3. 发明授权

US06461973B1 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects 失效
公开(公告)号：US06461973B1
公开(公告)日：2002-10-08
申请号：US09535256
申请日：2000-03-23
申请人： Angela T. Hui , Jusuke Ogura
发明人： Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21302
CPC分类号： H01L21/0206 , H01L21/28273 , H01L21/31116 , H01L21/31138 , H01L21/31662 , H01L21/823462
摘要： A method for forming high quality oxide layers having different thicknesses by eliminating descum induced defects is disclosed. A semiconductor substrate is subjected to reactive ion etching. The semiconductor substrate includes a wafer, an oxide layer on the wafer, a developed photoresist mask on the oxide layer. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

4. 发明授权

US06432618B1 Method for forming high quality multiple thickness oxide layers by reducing descum induced defects 有权
标题翻译：通过减少除锈引起的缺陷形成高质量多层氧化层的方法
公开(公告)号：US06432618B1
公开(公告)日：2002-08-13
申请号：US09535255
申请日：2000-03-23
申请人： Angela T. Hui , Jusuke Ogura
发明人： Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21302
CPC分类号： H01L21/823462 , H01L21/31138
摘要： A method for forming high quality oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, developing the photoresist layer to expose a region of the oxide layer. The substrate is then descummed to remove any residue resulting from the development of the photoresist. Following the descum process, the substrate is rinsed in water. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.
摘要翻译：一种通过消除除去诱导缺陷来形成具有不同厚度的高质量氧化物层的方法。该方法包括形成氧化物层，用光致抗蚀剂层掩蔽氧化物层，显影光致抗蚀剂层以暴露氧化物层的区域。然后除去基材以除去由光致抗蚀剂显影产生的残留物。在除去过程之后，将基底在水中漂洗。然后蚀刻氧化物层，并且在衬底上生长另一层氧化物之前剥离剩余的光致抗蚀剂。

5. 发明授权

US06617215B1 Memory wordline hard mask 有权
标题翻译：内存字线硬掩模
公开(公告)号：US06617215B1
公开(公告)日：2003-09-09
申请号：US10109235
申请日：2002-03-27
申请人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
发明人： Arvind Halliyal , Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey A. Shields , Jean Y. Yang , Emmanuil Lingunis , Angela T. Hui , Jusuke Ogura
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/0332 , H01L21/32139 , H01L27/115
摘要： A manufacturing method for a MirrorBit® Flash memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric material. First and second bitlines are implanted and a wordline material is deposited. A hard mask material is deposited over the wordline material. The hard mask material is of a material having the characteristic of being deposited rather than grown. A photoresist material is deposited over the wordline material and is patterned to form a patterned hard mask. The patterned photoresist material is removed. The wordline material is processed using the patterned hard mask to form a wordline. The patterned hard mask material is removed.
摘要翻译：用于MirrorBit（R）闪存的制造方法包括提供半导体衬底和沉积电荷俘获电介质材料。植入第一和第二位线，并存放字线材料。硬掩模材料沉积在字线材料上。硬掩模材料是具有沉积而不是生长的特征的材料。光致抗蚀剂材料沉积在字线材料上并被图案化以形成图案化的硬掩模。去除图案化的光致抗蚀剂材料。使用图案化的硬掩模处理字线材料以形成字线。去除图案化的硬掩模材料。

6. 发明申请

US20070262412A1 Avoiding Field Oxide Gouging In Shallow Trench Isolation (STI) Regions 审中-公开
标题翻译：在浅沟槽隔离（STI）区域避免场氧化物气刨
公开(公告)号：US20070262412A1
公开(公告)日：2007-11-15
申请号：US11781551
申请日：2007-07-23
申请人： Angela Hui , Jusuke Ogura , Yider Wu
发明人： Angela Hui , Jusuke Ogura , Yider Wu
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.
摘要翻译：一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。可以在STI区域中蚀刻沟槽并填充绝缘材料。抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。可以将保护盖回蚀以暴露ARC层。然而，保护盖仍然覆盖并保护绝缘材料。通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

7. 发明申请

US20090215243A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090215243A1
公开(公告)日：2009-08-27
申请号：US12369859
申请日：2009-02-12
申请人： Jusuke Ogura , Hikaru Kokura , Hideyuki Kojima , Toru Anezaki , Hiroyuki Ogawa , Junichi Ariyoshi
发明人： Jusuke Ogura , Hikaru Kokura , Hideyuki Kojima , Toru Anezaki , Hiroyuki Ogawa , Junichi Ariyoshi
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/823481 , H01L27/1052 , H01L27/11521
摘要： A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成限定有源区的隔离区，在半导体衬底上形成第一绝缘膜，形成第二绝缘膜，该第二绝缘膜具有与第一绝缘膜相同的蚀刻性能绝缘膜，通过使用基于碳氟化合物的蚀刻气体的干蚀刻从有源区域和隔离区域上的第一区域选择性地去除第二绝缘膜，通过在第一绝缘膜上暴露于第一绝缘膜上形成的残留膜含氧的气氛，通过湿式蚀刻从第一区域选择性地除去第一绝缘膜。

8. 发明申请

US20100270623A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD 有权
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20100270623A1
公开(公告)日：2010-10-28
申请号：US12761516
申请日：2010-04-16
申请人： Tomoyuki Kirimura , Jusuke Ogura
发明人： Tomoyuki Kirimura , Jusuke Ogura
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823871 , H01L21/823807 , H01L29/7843
摘要： A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor.
摘要翻译：一种半导体器件制造方法，包括：形成包括第一区域中的晶体管的栅极和第二区域中的晶体管的栅极的栅极导体，以及用于覆盖晶体管的第一应力膜上的第一膜; 通过使用掩模层从所述第二区域蚀刻所述第一膜，并且在所述掩模层的下面沿着与所述半导体衬底的表面平行的方向从所述第一掩模层的边缘以第一宽度蚀刻所述第一膜，并且所述第一应力第二区电影; 形成覆盖所述第一应力膜和所述第一膜的第二应力膜; 蚀刻第二应力膜，使得第二应力膜的一部分与第一应力膜的一部分和第一膜的一部分重叠; 并形成与栅极导体连接的接触孔。

9. 发明授权

US07199426B2 Nonvolatile semiconductor memory device and method for fabricating the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07199426B2
公开(公告)日：2007-04-03
申请号：US11076063
申请日：2005-03-10
申请人： Jusuke Ogura , Hiroyuki Ogawa , Tatsuo Chijimatsu
发明人： Jusuke Ogura , Hiroyuki Ogawa , Tatsuo Chijimatsu
IPC分类号： H01L29/72
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/42324 , H01L29/4238 , H01L29/792
摘要： The nonvolatile semiconductor memory device comprises a channel region formed in a semiconductor substrate, a gate electrode formed over the channel region with a charge retaining insulating film interposed therebetween, a first pair of source/drain regions arranged in a first direction with the channel region formed therebetween, and a second pair of source/drain regions arranged in a second direction intersecting the first direction with the channel region formed therebetween. The channel region and the gate electrode are common between a first memory cell transistor including the first pair of source/drain regions and a second memory cell transistor including the second pair of source/drain regions.
摘要翻译：非易失性半导体存储器件包括形成在半导体衬底中的沟道区，栅电极，形成在沟道区上，其间具有电荷保持绝缘膜，第一对源极/漏极区沿第一方向排列，形成沟道区以及沿与第一方向相交的第二方向布置的第二对源/漏区，其间形成有沟道区。沟道区域和栅电极在包括第一对源极/漏极区域的第一存储单元晶体管和包括第二对源极/漏极区域的第二存储单元晶体管之间是共同的。

10. 发明授权

US06828199B2 Monos device having buried metal silicide bit line 有权
标题翻译：具有埋置金属硅化物位线的单体器件
公开(公告)号：US06828199B2
公开(公告)日：2004-12-07
申请号：US10022798
申请日：2001-12-20
申请人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
发明人： Jusuke Ogura , Mark T. Ramsbey , Arvind Halliyal , Zoran Krivokapic , Minh Van Ngo , Nicholas H. Tripisas
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L21/743 , H01L27/115 , H01L29/66833 , H01L29/792
摘要： A MONOS device and method for making the device has a charge trapping dielectric layer, such as an oxide-nitride-oxide (ONO) layer, formed on a substrate. A recess is created through the ONO layer and in the substrate. A metal silicide bit line is formed in the recess and bit line oxide is formed on top of the metal silicide. A word line is formed over the ONO layer and the bit line oxide, and a low resistance silicide is provided on top of the word line. The silicide is formed by laser thermal annealing, for example.
摘要翻译：用于制造该器件的MONOS器件和方法具有形成在衬底上的电荷捕获介电层，例如氧化物 - 氮化物 - 氧化物（ONO）层。通过ONO层和衬底产生凹陷。在凹部中形成金属硅化物位线，并且在金属硅化物的顶部上形成位线氧化物。在ONO层和位线氧化物之间形成字线，并且在字线的顶部提供低电阻硅化物。硅化物例如由激光热退火形成。

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