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1. 发明授权

US07238571B1 Non-volatile memory device with increased reliability 有权
标题翻译：非易失性存储器件具有更高的可靠性
公开(公告)号：US07238571B1
公开(公告)日：2007-07-03
申请号：US11063560
申请日：2005-02-24
申请人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
发明人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.
摘要翻译：存储器件可以包括多个存储器单元，形成在存储器单元上的第一层间电介质和形成在层间电介质上的至少一个金属层。介电层可以形成在金属层的上方。电介质层可以表示在存储器件的上表面处或附近形成的覆盖层，并且可以在相对低的温度下沉积。

2. 发明授权

US07927723B1 Film stacks to prevent UV-induced device damage 有权
标题翻译：电影堆叠以防止紫外线引起的设备损坏
公开(公告)号：US07927723B1
公开(公告)日：2011-04-19
申请号：US11091524
申请日：2005-03-29
申请人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
发明人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
IPC分类号： G02B1/10 , G02B5/28 , B32B9/00 , B32B19/00
CPC分类号： G02B5/208
摘要： A film stack includes an interlayer dielectric formed over one or more devices. The film stack further includes a first layer having a high extinction coefficient formed on the interlayer dielectric and a second layer having a low extinction coefficient formed on the first layer. The first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.
摘要翻译：膜堆叠包括在一个或多个器件上形成的层间电介质。薄膜叠层还包括形成在层间电介质上的具有高消光系数的第一层和形成在第一层上的具有低消光系数的第二层。第一层和第二层防止对一种或多种设备的紫外线诱发的损坏，同时最小化光刻工艺的反射率。

3. 发明授权

US08367493B1 Void free interlayer dielectric 有权
标题翻译：无空隙层间电介质
公开(公告)号：US08367493B1
公开(公告)日：2013-02-05
申请号：US11109719
申请日：2005-04-20
申请人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
发明人： Minh Van Ngo , Hirokazu Tokuno , Angela T. Hui , Wenmei Li , Hsiao-Han Thio
IPC分类号： H01L21/8238
CPC分类号： H01L23/291 , H01L21/823425 , H01L21/823475 , H01L27/11521 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.
摘要翻译：一种制造非易失性存储器件的方法包括形成多个存储单元。该方法还包括在存储器单元上沉积第一介电层，其中第一介电层是具有基本均匀厚度的共形层。该方法还包括在第一介电层上沉积第二电介质层。第一和第二电介质层一起形成没有空隙的层间电介质。

4. 发明授权

US07704878B2 Contact spacer formation using atomic layer deposition 有权
标题翻译：使用原子层沉积接触间隔物形成
公开(公告)号：US07704878B2
公开(公告)日：2010-04-27
申请号：US11240468
申请日：2005-10-03
申请人： Minh Van Ngo , Angela T. Hui , Amol Ramesh Joshi , Wenmei Li , Ning Cheng , Ankur Bhushan Agarwal , Norimitsu Takagi
发明人： Minh Van Ngo , Angela T. Hui , Amol Ramesh Joshi , Wenmei Li , Ning Cheng , Ankur Bhushan Agarwal , Norimitsu Takagi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.
摘要翻译：半导体器件中的接触结构包括介电材料层和通过介电材料形成的通孔。接触结构还包括通过使用原子层沉积（ALD）和沉积在通孔中的金属在通孔的侧壁上形成的间隔物。

5. 发明授权

US07300886B1 Interlayer dielectric for charge loss improvement 有权
标题翻译：用于电荷损耗改善的层间电介质
公开(公告)号：US07300886B1
公开(公告)日：2007-11-27
申请号：US11147208
申请日：2005-06-08
申请人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
发明人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
IPC分类号： H01L21/31
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L27/115 , H01L27/11568
摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.
摘要翻译：一种制造存储器件的方法包括在衬底上形成第一介电层，并在第一介电层上形成电荷存储元件。该方法还包括在电荷存储元件上形成第二电介质层，并在第二电介质层上形成控制栅极。该方法还包括在高温下在控制栅极上沉积层间电介质。

6. 发明授权

US08564041B2 Contacts for semiconductor devices 有权
标题翻译：半导体器件的触点
公开(公告)号：US08564041B2
公开(公告)日：2013-10-22
申请号：US11551532
申请日：2006-10-20
申请人： Angela T. Hui , Wenmei Li , Minh Van Ngo , Amol Ramesh Joshi , Kuo-Tung Chang
发明人： Angela T. Hui , Wenmei Li , Minh Van Ngo , Amol Ramesh Joshi , Kuo-Tung Chang
IPC分类号： H01L27/108
CPC分类号： H01L29/78 , H01L27/115 , H01L27/11568
摘要： A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.
摘要翻译：存储器件包括多个存储单元和形成在存储单元上的电介质层。存储器件还包括形成在电介质层中的触点和邻近触头的侧表面形成的间隔件。间隔物可以抑制来自接触件的泄漏电流。

7. 发明授权

US08022468B1 Ultraviolet radiation blocking interlayer dielectric 有权
标题翻译：紫外辐射阻挡层间电介质
公开(公告)号：US08022468B1
公开(公告)日：2011-09-20
申请号：US11091519
申请日：2005-03-29
申请人： Minh Van Ngo , Wenmei Li , Jeffrey A. Shields , Ning Cheng , Angela Hui , Cinti Xiaohua Chen
发明人： Minh Van Ngo , Wenmei Li , Jeffrey A. Shields , Ning Cheng , Angela Hui , Cinti Xiaohua Chen
IPC分类号： H01L29/66
CPC分类号： H01L27/11521 , H01L23/552 , H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.
摘要翻译：存储器件可以包括衬底，形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二介电层和形成在第二介电层上的控制栅极。存储器件还可以包括在控制栅极和衬底上形成的层间电介质，其中层间电介质包括对紫外线辐射基本不透明的材料。

8. 发明申请

US20060214218A1 Semiconductor device and method of fabricating the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060214218A1
公开(公告)日：2006-09-28
申请号：US11258823
申请日：2005-10-25
申请人： Kiyokazu Shishido , Masahiko Higashi , Minh Ngo , Angela Hui , Wenmei Li , Ning Cheng , Mark Ramsbey , Hirokazu Tokuno , Pei-Yuan Gao , Takayuki Enda
发明人： Kiyokazu Shishido , Masahiko Higashi , Minh Ngo , Angela Hui , Wenmei Li , Ning Cheng , Mark Ramsbey , Hirokazu Tokuno , Pei-Yuan Gao , Takayuki Enda
IPC分类号： H01L29/792
CPC分类号： H01L21/76801 , H01L21/02129 , H01L21/022 , H01L21/3144 , H01L21/31625 , H01L21/76829 , H01L27/11568 , H01L29/40117 , H01L29/513
摘要： A semiconductor device includes a semiconductor substrate, an ONO film that is provided on the semiconductor substrate and has a contact hole, and an interlayer insulating film that is provided directly on the ONO film and contains phosphorus. The interlayer insulating film contains 4.5 wt % of phosphorus or more in an interface portion that interfaces with the ONO film. The interlayer insulating film comprises a first portion that contacts the ONO film, and a second portion provided on the first portion. The first portion has a phosphorus concentration more than that of the second portion.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上并具有接触孔的ONO膜，以及直接设置在ONO膜上并含有磷的层间绝缘膜。在与ONO膜接合的界面部分中，层间绝缘膜含有4.5重量％以上的磷。层间绝缘膜包括接触ONO膜的第一部分和设置在第一部分上的第二部分。第一部分的磷浓度大于第二部分的磷浓度。

9. 发明授权

US06613657B1 BPSG, SA-CVD liner/P-HDP gap fill 有权
标题翻译： BPSG，SA-CVD衬垫/ P-HDP间隙填充
公开(公告)号：US06613657B1
公开(公告)日：2003-09-02
申请号：US10231133
申请日：2002-08-30
申请人： Minh Van Ngo , Dawn Hopper , Wenmei Li , Kelwin King Wai Ko , Kuo-Tung Chang , Tyagamohan Gottipati
发明人： Minh Van Ngo , Dawn Hopper , Wenmei Li , Kelwin King Wai Ko , Kuo-Tung Chang , Tyagamohan Gottipati
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115
摘要： Device leakage due to spacer undercutting is remedied by depositing a BPSG, SA-CVD oxide liner and flowing it into the undercut regions, followed by gap filling with a P-doped HDP oxide layer. Embodiments include depositing a BPSG, SA-CVD oxide liner containing 4 to 6 wt.% boron, at a thickness of 1,000 Å to 1,800 Å, over closely spaced apart non-volatile transistors and heating during or subsequent to deposition to flow the BPSG, SA-CVD oxide liner into the undercut regions of the sidewall spacers of the gate stacks. Gap filling is then completed by depositing the layer of P-doped HDP at a thickness of 6,000 Å to 10,000 Å.
摘要翻译：通过沉积BPSG，SA-CVD氧化物衬垫并将其流入底切区域，随后用P掺杂的HDP氧化物层填充间隙来补救由间隔物底切造成的器件泄漏。实施方案包括在紧密间隔开的非易失性晶体管上沉积厚度为1,000至1,800的含有4至6重量％硼的BPSG，SA-CVD氧化物衬垫，并在沉积期间或之后加热以使BPSG流动， SA-CVD氧化物衬垫进入栅堆叠的侧壁间隔物的底切区域。然后通过沉积厚度为6,000至10,000的P掺杂HDP层完成间隙填充。

10. 发明授权

US07572727B1 Semiconductor formation method that utilizes multiple etch stop layers 有权
标题翻译：利用多个蚀刻停止层的半导体形成方法
公开(公告)号：US07572727B1
公开(公告)日：2009-08-11
申请号：US10934828
申请日：2004-09-02
申请人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
发明人： Wenmei Li , Angela T. Hui , Dawn Hopper , Kouros Ghandehari
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , H01L21/76804 , H01L21/76829 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
摘要翻译：本发明是一种半导体接触形成系统和方法。接触绝缘区域形成有多个有助于形成接触的蚀刻停止子层。该接触形成工艺提供了相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。在一个实施例中，沉积包括多个蚀刻停止层的多次蚀刻停止绝缘层。通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除在金属层附近，并且更靠近基底的部分被去除。通过在多个蚀刻停止绝缘层中由多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现不同的接触区域宽度。导电材料（例如，钨）沉积在接触区域中。

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