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51. 发明授权

US07893456B1 Thyristor-based memory and its method of operation 失效
标题翻译：基于晶闸管的存储器及其操作方法
公开(公告)号：US07893456B1
公开(公告)日：2011-02-22
申请号：US12368226
申请日：2009-02-09
申请人： Farid Nemati , Kevin J. Yang
发明人： Farid Nemati , Kevin J. Yang
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.
摘要翻译：基于晶闸管的存储器可以包括通过存取晶体管可访问的晶闸管。可以将温度依赖偏压施加到电容耦合到晶闸管的基极区域的支撑衬底和电极中的至少一个。自适应偏置的电压电平可以相对于温度而变化，并且可以根据偏置的变化影响和/或补偿晶闸管的固有双极增益，并且可以在一定范围的工作温度下增强其性能和/或可靠性。在特定实施例中，晶闸管可以形成在SOI衬底的硅层中，并且耦合到SOI结构的支撑衬底的自适应偏置。

52. 发明授权

US07379381B1 State maintenance pulsing for a memory device 失效
标题翻译：用于存储设备的状态维护脉冲
公开(公告)号：US07379381B1
公开(公告)日：2008-05-27
申请号：US11175057
申请日：2005-07-05
申请人： Richard Roy , Farid Nemati
发明人： Richard Roy , Farid Nemati
IPC分类号： G11C8/00
CPC分类号： G11C11/404 , G11C11/406 , G11C11/40622
摘要： State maintenance of a memory cell and, more particularly, state maintenance pulsing of identified memory cells more frequently than other memory cells, is described. A memory array includes an array of memory cells. State maintenance circuitry is coupled to the array of memory cells. The state maintenance circuitry is configured to select between a first restore address and a second restore address. In a given operation cycle, the first restore address is associated with a first line in the array of memory cells, and the second restore address is associated with a second line in the array of memory cells. The first line has first memory cells coupled thereto. The second line has second memory cells coupled thereto. The first memory cells are capable of passing a threshold retention time with a first frequency of restore cycling. The second memory cells are capable of passing the threshold retention time with a second frequency of restore cycling. The second frequency of restore cycling is greater than the first frequency of restore cycling.
摘要翻译：描述了存储器单元的状态维护，更具体地，描述了比其他存储器单元更频繁地状态维持所标识的存储器单元的脉冲。存储器阵列包括存储器单元阵列。状态维护电路耦合到存储器单元阵列。状态维护电路被配置为在第一恢复地址和第二恢复地址之间进行选择。在给定的操作周期中，第一恢复地址与存储器单元阵列中的第一行相关联，并且第二恢复地址与存储器单元阵列中的第二行相关联。第一行具有耦合到其上的第一存储单元。第二行具有与其耦合的第二存储单元。第一存储器单元能够以第一恢复循环频率通过阈值保持时间。第二存储器单元能够以第二恢复循环频率通过阈值保持时间。恢复循环的第二个频率大于恢复循环的第一个频率。

53. 发明授权

US07365373B2 Thyristor-type memory device 失效
标题翻译：晶闸管型存储器件
公开(公告)号：US07365373B2
公开(公告)日：2008-04-29
申请号：US11206627
申请日：2005-08-18
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L29/423
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
摘要翻译：晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置低电导状态和/或从低电导状态到高电导状态。可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

54. 发明授权

US07304327B1 Thyristor circuit and approach for temperature stability 失效
标题翻译：晶闸管电路和温度稳定性方法
公开(公告)号：US07304327B1
公开(公告)日：2007-12-04
申请号：US10706162
申请日：2003-11-12
申请人： Farid Nemati , Kailash Gopalakrishnan , Andrew E. Horch
发明人： Farid Nemati , Kailash Gopalakrishnan , Andrew E. Horch
IPC分类号： H01L29/745
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： Switching operations, such as those used in memory devices, are enhanced using a semiconductor device having a thyristor adapted to switch between conducting and blocking states and operate at low power. According to an example embodiment of the present invention, thyristor characteristics are managed over a broad temperature range using a control circuit for coupling a signal, such as a DC voltage signal, to a portion of a thyristor for controlling temperature-related operation thereof, e.g., for controlling bipolar gains. In one implementation, a control port adaptively adjusts a signal coupled to the thyristor as a function of temperature, such that at relatively low temperatures unwanted increases in holding current (IH) are prevented. In another implementation, the control port couples the signal at relatively high temperature operation for controlling the forward blocking voltage (VFB) in such a manner that a blocking state of the thyristor is held. In still another implementation, a circuit controller is adapted for applying the signal to the thyristor via the control port as a function of temperature by monitoring operation of a reference thyristor. With these approaches, thyristor operation can be maintained in a relatively stable manner over a broad temperature range.
摘要翻译：使用具有适于在导通和阻塞状态之间切换并且以低功率操作的晶闸管的半导体器件来增强诸如存储器件中使用的切换操作。根据本发明的示例性实施例，使用用于将诸如DC电压信号的信号耦合到用于控制其温度相关操作的晶闸管的一部分的控制电路，在宽温度范围内管理晶闸管特性，例如，用于控制双极增益。在一个实施方案中，控制端口自适应地调节作为温度的函数耦合到晶闸管的信号，使得在相对较低的温度下，防止了保持电流（I H H）的不期望的增加。在另一实施方案中，控制端口以相对较高的温度操作耦合信号，以便控制可控硅晶闸管的阻塞状态的方式来控制正向阻断电压（V SUB FB）。在另一个实施方式中，电路控制器适于通过监视参考晶闸管的操作，通过控制端口将信号作为温度的函数施加到晶闸管。利用这些方法，可以在宽的温度范围内以相对稳定的方式保持晶闸管操作。

55. 发明申请

US20060011940A1 Thyristor-type memory device 失效
标题翻译：晶闸管型存储器件
公开(公告)号：US20060011940A1
公开(公告)日：2006-01-19
申请号：US11206627
申请日：2005-08-18
申请人： Farid Nemati , James Plummer
发明人： Farid Nemati , James Plummer
IPC分类号： H01L29/423
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.
摘要翻译：晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置低电导状态和/或从低电导状态到高电导状态。可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

56. 发明授权

US06448586B1 Semiconductor current-switching device having operational enhancer and method therefor 有权
标题翻译：具有操作增强器的半导体电流开关器件及其方法
公开(公告)号：US06448586B1
公开(公告)日：2002-09-10
申请号：US09666825
申请日：2000-09-21
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L2974
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other type of NDR-based SRAMs.
摘要翻译：可以使用新颖的电容耦合NDR器件来实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，NDR设备用作具有电容耦合门辅助关断和导通机制的薄垂直PNPN结构。基于这种新器件的SRAM在单元面积，待机电流，架构，速度和制造工艺方面相当于相同容量的DRAM。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，具有8F2封装，可以在高速和低电压下工作，具有良好的噪声余量，并且与主流CMOS的制造工艺兼容。与其他类型的基于NDR的SRAM相比，该单元显着降低了待机功耗。

57. 发明授权

US08519431B2 Thyristors 有权
公开(公告)号：US08519431B2
公开(公告)日：2013-08-27
申请号：US13043295
申请日：2011-03-08
申请人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
发明人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
IPC分类号： H01L29/74
CPC分类号： G11C11/39 , H01L21/28008 , H01L21/30604 , H01L21/76224 , H01L27/0817 , H01L27/1027 , H01L29/7455 , H01L29/749
摘要： Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

58. 发明授权

US08441881B1 Tracking for read and inverse write back of a group of thyristor-based memory cells 失效
标题翻译：跟踪一组基于晶闸管的存储单元的读和反写入
公开(公告)号：US08441881B1
公开(公告)日：2013-05-14
申请号：US13172630
申请日：2011-06-29
申请人： Farid Nemati
发明人： Farid Nemati
IPC分类号： G11C5/14
CPC分类号： G11C11/39
摘要： Method and integrated circuit for tracking for read and inverse write back of a group of thyristor-based memory cells is described. The method includes: reading the group of memory cells to obtain read data, and writing back opposite data states for the read data to the group of memory cells. The group of memory cells includes data cells and at least one check cell for check data, where the check data indicates polarity of the read data. The integrated circuit includes a grouping of memory cells of an array of memory cells including data cells and at least one check cell, and sense amplifiers. The at least one check cell is to track inversion/non-inversion status of the data cells associated therewith, and the sense amplifiers are coupled to obtain read information from the grouping and to write back data states opposite of those of the read information.
摘要翻译：描述了用于跟踪一组基于晶闸管的存储器单元的读取和反向写回的方法和集成电路。该方法包括：读取存储器单元组以获得读取数据，并将读取的数据的相反数据状态写回存储器单元组。该组存储器单元包括数据单元和用于检查数据的至少一个检验单元，其中检查数据指示读取数据的极性。集成电路包括存储单元阵列的存储单元组，包括数据单元和至少一个校验单元以及读出放大器。所述至少一个检验单元是跟踪与其相关联的数据单元的反转/非反转状态，并且读出放大器被耦合以从分组获得读取信息并写回与读取信息的数据状态相反的数据状态。

59. 发明授权

US07961540B2 Dynamic data restore in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件中的动态数据恢复
公开(公告)号：US07961540B2
公开(公告)日：2011-06-14
申请号：US12182128
申请日：2008-07-29
申请人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
发明人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
IPC分类号： G11C11/00
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
摘要翻译：使用动态操作的恢复电路将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元，并且其中使用晶闸管的内部正反馈回路在单元中恢复数据。在一个示例实现中，晶闸管中的内部正反馈环路用于在晶闸管电流下降到保持电流以下之前恢复器件的导通状态。定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用稳定存储元件

60. 发明申请

US20100315871A1 DYNAMIC DATA RESTORE IN THYRISTOR-BASED MEMORY DEVICE 失效
标题翻译：基于存储器的存储器件中的动态数据恢复
公开(公告)号：US20100315871A1
公开(公告)日：2010-12-16
申请号：US12182128
申请日：2008-07-29
申请人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
发明人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
IPC分类号： G11C11/34
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
摘要翻译：使用动态操作的恢复电路将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元，并且其中使用晶闸管的内部正反馈回路在单元中恢复数据。在一个示例实现中，晶闸管中的内部正反馈环路用于在晶闸管电流下降到保持电流以下之前恢复器件的导通状态。定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用稳定存储元件

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