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51. 发明授权

US07488627B1 Thyristor-based memory and its method of operation 失效
标题翻译：基于晶闸管的存储器及其操作方法
公开(公告)号：US07488627B1
公开(公告)日：2009-02-10
申请号：US11487548
申请日：2006-07-15
申请人： Farid Nemati , Kevin J. Yang
发明人： Farid Nemati , Kevin J. Yang
IPC分类号： H01L21/332
CPC分类号： G11C11/39 , H01L29/7436 , H01L29/749
摘要： A thyristor-based memory may comprise a thyristor accessible via an access transistor. A temperature dependent bias may be applied to at least one of a supporting substrate and an electrode capacitively-coupled to a base region of the thyristor. The voltage level of the adaptive bias may change with respect to temperature and may influence and/or compensate an inherent bipolar gain of the thyristor in accordance with the change in bias and may enhance its performance and/or reliability over a range of operating temperature. In a particular embodiment, the thyristor may be formed in a layer of silicon of an SOI substrate and the adaptive bias coupled to a supporting substrate of the SOI structure.
摘要翻译：基于晶闸管的存储器可以包括通过存取晶体管可访问的晶闸管。可以将温度依赖偏压施加到电容耦合到晶闸管的基极区域的支撑衬底和电极中的至少一个。自适应偏置的电压电平可以相对于温度而变化，并且可以根据偏置的变化影响和/或补偿晶闸管的固有双极增益，并且可以在一定范围的工作温度下增强其性能和/或可靠性。在特定实施例中，晶闸管可以形成在SOI衬底的硅层中，并且耦合到SOI结构的支撑衬底的自适应偏置。

52. 发明申请

US20060139996A1 Dynamic data restore in thyristor-based memory device 失效
公开(公告)号：US20060139996A1
公开(公告)日：2006-06-29
申请号：US11361334
申请日：2006-02-24
申请人： Farid Nemati , Hyun-jin Cho , Robert Igehy
发明人： Farid Nemati , Hyun-jin Cho , Robert Igehy
IPC分类号： G11C11/34
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

53. 发明授权

US07042759B2 Dynamic data restore in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件中的动态数据恢复
公开(公告)号：US07042759B2
公开(公告)日：2006-05-09
申请号：US11112090
申请日：2005-04-22
申请人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
发明人： Farid Nemati , Hyun-Jin Cho , Robert Homan Igehy
IPC分类号： G11C11/00
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
摘要翻译：使用动态操作的恢复电路将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元，并且其中使用晶闸管的内部正反馈回路在单元中恢复数据。在一个示例实现中，晶闸管中的内部正反馈环路用于在晶闸管电流下降到保持电流以下之前恢复器件的导通状态。定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用稳定存储元件

54. 发明申请

US20050185489A1 Dynamic data restore in thyristor-based memory device 失效
标题翻译：基于晶闸管的存储器件中的动态数据恢复
公开(公告)号：US20050185489A1
公开(公告)日：2005-08-25
申请号：US11112090
申请日：2005-04-22
申请人： Farid Nemati , Hyun-Jin Cho , Robert Igehy
发明人： Farid Nemati , Hyun-Jin Cho , Robert Igehy
IPC分类号： G11C7/00 , G11C11/00 , G11C11/39 , H01L29/866
CPC分类号： G11C11/39
摘要： A dynamically-operating restoration circuit is used to apply a voltage or current restore pulse signal to thyristor-based memory cells and therein restore data in the cell using the internal positive feedback loop of the thyristor. In one example implementation, the internal positive feedback loop in the thyristor is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.
摘要翻译：使用动态操作的恢复电路将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元，并且其中使用晶闸管的内部正反馈回路在单元中恢复数据。在一个示例实现中，晶闸管中的内部正反馈环路用于在晶闸管电流下降到保持电流以下之前恢复器件的导通状态。定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用稳定存储元件

55. 发明授权

US06727529B2 Semiconductor capacitively-coupled NDR device and related applications in high-density high-speed memories and in power switches 失效
标题翻译：半导体电容耦合NDR器件及相关应用在高密度高速存储器和电源开关中
公开(公告)号：US06727529B2
公开(公告)日：2004-04-27
申请号：US10103241
申请日：2002-03-20
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L2974
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
摘要翻译：可以使用新颖的电容耦合NDR器件来实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，NDR设备用作具有电容耦合门辅助关断和导通机制的薄垂直PNPN结构。基于这种新器件的SRAM在单元面积，待机电流，架构，速度和制造工艺方面相当于相同容量的DRAM。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，具有8F 2的占位面积，可以在高速和低电压下工作，具有良好的噪声容限，并且与主 - 流CMOS。与其他类型的基于NDR的SRAM相比，该单元显着降低了待机功耗。

56. 发明授权

US06229161B1 Semiconductor capacitively-coupled NDR device and its applications in high-density high-speed memories and in power switches 失效
标题翻译：半导体电容耦合NDR器件及其在高密度高速存储器和电源开关中的应用
公开(公告)号：US06229161B1
公开(公告)日：2001-05-08
申请号：US09092449
申请日：1998-06-05
申请人： Farid Nemati , James D. Plummer
发明人： Farid Nemati , James D. Plummer
IPC分类号： H01L2974
CPC分类号： H01L29/74 , G11C11/39 , H01L27/0617 , H01L27/0688 , H01L27/1023 , H01L27/1027 , H01L27/11 , H01L27/1104 , H01L29/41716 , H01L29/42308 , H01L29/749 , H01L29/87
摘要： A novel capacitively coupled NDR device can be used to implement a variety of semiconductor circuits, including high-density SRAM cells and power thyristor structures. In one example embodiment, the NDR device is used as a thin vertical PNPN structure with capacitively-coupled gate-assisted turn-off and turn-on mechanisms. An SRAM based on this new device is comparable in cell area, standby current, architecture, speed, and fabrication process to a DRAM of the same capacity. In one embodiment, an NDR-based SRAM cell consists of only two elements, has an 8 F2 footprint, can operate at high speeds and low voltages, has a good noise-margin, and is compatible in fabrication process with main-stream CMOS. This cell significantly reduces standby power consumption compared to other types of NDR-based SRAMs.
摘要翻译：可以使用新颖的电容耦合NDR器件来实现各种半导体电路，包括高密度SRAM单元和功率晶闸管结构。在一个示例实施例中，NDR设备用作具有电容耦合门辅助关断和导通机制的薄垂直PNPN结构。基于这种新器件的SRAM在单元面积，待机电流，架构，速度和制造工艺方面相当于相同容量的DRAM。在一个实施例中，基于NDR的SRAM单元仅由两个元件组成，具有8F2封装，可以在高速和低电压下工作，具有良好的噪声余量，并且与主流CMOS的制造工艺兼容。与其他类型的基于NDR的SRAM相比，该单元显着降低了待机功耗。

57. 发明申请

US20190198083A1 Memory System Having Combined High Density, Low Bandwidth and Low Density, High Bandwidth Memories 审中-公开
公开(公告)号：US20190198083A1
公开(公告)日：2019-06-27
申请号：US16098916
申请日：2017-03-06
申请人： Sukalpa Biswasw , Farid Nemati
发明人： Sukalpa Biswas , Farid Nemati
IPC分类号： G11C11/402 , G11C11/406 , G11C5/06
摘要： In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

58. 发明授权

US08952418B2 Gated bipolar junction transistors 有权
标题翻译：门极双极结晶体管
公开(公告)号：US08952418B2
公开(公告)日：2015-02-10
申请号：US13037642
申请日：2011-03-01
申请人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
发明人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
IPC分类号： H01L29/74 , H01L29/73 , H01L27/102 , H01L29/735 , H01L27/108 , H01L29/78
CPC分类号： H01L27/1026 , H01L21/02381 , H01L21/02529 , H01L21/8229 , H01L27/1023 , H01L27/1024 , H01L27/10802 , H01L29/1608 , H01L29/73 , H01L29/732 , H01L29/735 , H01L29/7391 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
摘要翻译：一些实施例包括门极双极结型晶体管。晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。一些实施例包括包含门极双极结型晶体管的存储器阵列。一些实施例包括形成门控双极结型晶体管的方法。

59. 发明申请

US20120228629A1 Thyristors, Methods of Programming Thyristors, and Methods of Forming Thyristors 有权
标题翻译：晶闸管，晶闸管编程方法和形成晶闸管的方法
公开(公告)号：US20120228629A1
公开(公告)日：2012-09-13
申请号：US13043295
申请日：2011-03-08
申请人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
发明人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
IPC分类号： H01L29/74 , H01L21/8229 , H01L21/22
CPC分类号： G11C11/39 , H01L21/28008 , H01L21/30604 , H01L21/76224 , H01L27/0817 , H01L27/1027 , H01L29/7455 , H01L29/749
摘要： Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
摘要翻译：一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。第二基极区域在第三结区与第二电极区域相接合。栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。一些实施例包括编程晶闸管的方法，并且一些实施例包括形成晶闸管的方法。

60. 发明申请

US20120223369A1 Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors 有权
标题翻译：门极双极结晶体管，存储器阵列和形成门极双极结晶体管的方法
公开(公告)号：US20120223369A1
公开(公告)日：2012-09-06
申请号：US13037642
申请日：2011-03-01
申请人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
发明人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
IPC分类号： H01L23/52 , H01L21/331 , H01L29/73
CPC分类号： H01L27/1026 , H01L21/02381 , H01L21/02529 , H01L21/8229 , H01L27/1023 , H01L27/1024 , H01L27/10802 , H01L29/1608 , H01L29/73 , H01L29/732 , H01L29/735 , H01L29/7391 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
摘要翻译：一些实施例包括门极双极结型晶体管。晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。一些实施例包括包含门极双极结型晶体管的存储器阵列。一些实施例包括形成门控双极结型晶体管的方法。

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