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1. 发明授权

US08519431B2 Thyristors 有权
公开(公告)号：US08519431B2
公开(公告)日：2013-08-27
申请号：US13043295
申请日：2011-03-08
申请人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
发明人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
IPC分类号： H01L29/74
CPC分类号： G11C11/39 , H01L21/28008 , H01L21/30604 , H01L21/76224 , H01L27/0817 , H01L27/1027 , H01L29/7455 , H01L29/749
摘要： Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

2. 发明授权

US08952418B2 Gated bipolar junction transistors 有权
标题翻译：门极双极结晶体管
公开(公告)号：US08952418B2
公开(公告)日：2015-02-10
申请号：US13037642
申请日：2011-03-01
申请人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
发明人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
IPC分类号： H01L29/74 , H01L29/73 , H01L27/102 , H01L29/735 , H01L27/108 , H01L29/78
CPC分类号： H01L27/1026 , H01L21/02381 , H01L21/02529 , H01L21/8229 , H01L27/1023 , H01L27/1024 , H01L27/10802 , H01L29/1608 , H01L29/73 , H01L29/732 , H01L29/735 , H01L29/7391 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
摘要翻译：一些实施例包括门极双极结型晶体管。晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。一些实施例包括包含门极双极结型晶体管的存储器阵列。一些实施例包括形成门控双极结型晶体管的方法。

3. 发明申请

US20120228629A1 Thyristors, Methods of Programming Thyristors, and Methods of Forming Thyristors 有权
标题翻译：晶闸管，晶闸管编程方法和形成晶闸管的方法
公开(公告)号：US20120228629A1
公开(公告)日：2012-09-13
申请号：US13043295
申请日：2011-03-08
申请人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
发明人： Farid Nemati , Scott T. Robins , Rajesh N. Gupta
IPC分类号： H01L29/74 , H01L21/8229 , H01L21/22
CPC分类号： G11C11/39 , H01L21/28008 , H01L21/30604 , H01L21/76224 , H01L27/0817 , H01L27/1027 , H01L29/7455 , H01L29/749
摘要： Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
摘要翻译：一些实施例包括具有第一和第二电极区域，第一和第二基极区域以及在至少一个区域中具有至少1.2eV的带隙的材料的晶闸管。第一基极区域在第一电极区域和第二基极区域之间，第二基极区域在第二电极区域和第一基极区域之间。第一基区在第一结处与第一电极区相接，并且在第二结处与第二基区交界。第二基极区域在第三结区与第二电极区域相接合。栅极沿着第一基极区域，并且在一些实施例中不与第一和第二结点重叠。一些实施例包括编程晶闸管的方法，并且一些实施例包括形成晶闸管的方法。

4. 发明申请

US20120223369A1 Gated Bipolar Junction Transistors, Memory Arrays, and Methods of Forming Gated Bipolar Junction Transistors 有权
标题翻译：门极双极结晶体管，存储器阵列和形成门极双极结晶体管的方法
公开(公告)号：US20120223369A1
公开(公告)日：2012-09-06
申请号：US13037642
申请日：2011-03-01
申请人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
发明人： Rajesh N. Gupta , Farid Nemati , Scott T. Robins
IPC分类号： H01L23/52 , H01L21/331 , H01L29/73
CPC分类号： H01L27/1026 , H01L21/02381 , H01L21/02529 , H01L21/8229 , H01L27/1023 , H01L27/1024 , H01L27/10802 , H01L29/1608 , H01L29/73 , H01L29/732 , H01L29/735 , H01L29/7391 , H01L29/7841 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
摘要翻译：一些实施例包括门极双极结型晶体管。晶体管可以包括在集电极区域和发射极区域之间的基极区域; 其中B-C结位于基极区和集电极区的界面处，并且B-E结位于基极区和发射极区的界面处。晶体管可以包括在一个或多个基极，发射极和集电极区内具有至少1.2eV的带隙的材料。栅极晶体管可以包括沿着基极区域的栅极并且通过电介质材料与基极区域间隔开，栅极不与B-C结或B-E结重叠。一些实施例包括包含门极双极结型晶体管的存储器阵列。一些实施例包括形成门控双极结型晶体管的方法。

5. 发明申请

US20130182486A1 MEMORY CELLS HAVING A COMMON GATE TERMINAL 有权
公开(公告)号：US20130182486A1
公开(公告)日：2013-07-18
申请号：US13350061
申请日：2012-01-13
申请人： Rajesh N. Gupta , Farid Nemati
发明人： Rajesh N. Gupta , Farid Nemati
IPC分类号： G11C11/21 , H01L21/8239
CPC分类号： H01L27/2454 , G11C11/161 , G11C11/1659 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1608
摘要： Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.

6. 发明授权

US07491586B2 Semiconductor device with leakage implant and method of fabrication 失效
标题翻译：具有漏电注入的半导体器件及其制造方法
公开(公告)号：US07491586B2
公开(公告)日：2009-02-17
申请号：US11159514
申请日：2005-06-22
申请人： Andrew E Horch , Hyun-Jin Cho , Farid Nemati , Scott Robins , Rajesh N. Gupta , Kevin J. Yang
发明人： Andrew E Horch , Hyun-Jin Cho , Farid Nemati , Scott Robins , Rajesh N. Gupta , Kevin J. Yang
IPC分类号： H01L21/332 , H01L21/04 , H01L21/425
CPC分类号： G11C11/39 , H01L27/0817 , H01L29/7436 , H01L29/7455 , H01L29/749
摘要： A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.
摘要翻译：制造基于晶闸管的存储器的方法可以包括在硅中形成用于限定可控硅和串联连接的存取装置的不同的相反导电型区域。激活退火可以激活先前为不同区域植入的掺杂剂。可以将锗或氙或氩的有害植入物引导到硅的选择区域中，包括用于进入装置和晶闸管的至少一个p-n结区域。然后可以进行重结晶退火，以重新结晶由损伤性植入物引起的至少一些损伤的晶格结构。再结晶退火可以使用比先前激活退火的温度低的温度。

7. 发明授权

US09082494B2 Memory cells having a common gate terminal 有权
标题翻译：具有公共栅极端子的存储单元
公开(公告)号：US09082494B2
公开(公告)日：2015-07-14
申请号：US13350061
申请日：2012-01-13
申请人： Rajesh N. Gupta , Farid Nemati
发明人： Rajesh N. Gupta , Farid Nemati
IPC分类号： G11C11/00 , G11C11/16 , H01L45/00 , H01L27/22 , H01L27/24
CPC分类号： H01L27/2454 , G11C11/161 , G11C11/1659 , H01L27/228 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/141 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1608
摘要： Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.
摘要翻译：这里描述了具有公共栅极端子的存储单元阵列及其操作和形成方法。作为示例，存储器单元阵列可以包括一组存储器单元，每个存储单元具有耦合到选择器件的电阻存储元件。每个选择装置包括第一端子，第二端子和栅极端子，其中栅极端子对于该组的每个存储器单元是公用的。

8. 发明授权

US08174046B1 Reducing effects of parasitic transistors in thyristor-based memory using local thinning or implanting 失效
标题翻译：使用局部变薄或植入，减少寄生晶体管在基于晶闸管的存储器中的影响
公开(公告)号：US08174046B1
公开(公告)日：2012-05-08
申请号：US11362285
申请日：2006-02-23
申请人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
发明人： Marc Laurent Tarabbia , Maxim Ershov , Rajesh N. Gupta
IPC分类号： H01L29/74
CPC分类号： H01L29/66393 , H01L27/1027 , H01L27/105 , H01L29/7436
摘要： Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.
摘要翻译：描述了具有包括基于晶闸管的存储器单元的存储器的集成电路的方法和装置。一对基于晶闸管的存储单元通常经由位线区域耦合，其中响应于位线区域是共同的，限定了寄生双极结型晶体管。在另一个实施方案中，一对基于晶闸管的存储单元通常经由阳极区耦合，其中响应于阳极区域是共同的，限定了寄生双极结型晶体管。公共位线或阳极区域分别具有局部变薄的区域，以通过寄生双极结型晶体管抑制该对之间的电荷转移。此外，描述了在绝缘体上硅晶片上形成场效应晶体管的方法，其中响应于至少接近绝缘体层的掺杂剂的增加，由寄生双极晶体管促进电荷转移。

9. 发明申请

US20140003140A1 THYRISTOR MEMORY AND METHODS OF OPERATION 有权
标题翻译： THYRISTOR记忆和操作方法
公开(公告)号：US20140003140A1
公开(公告)日：2014-01-02
申请号：US13535048
申请日：2012-06-27
申请人： Rajesh N. Gupta
发明人： Rajesh N. Gupta
IPC分类号： G11C11/39
CPC分类号： G11C11/39 , B82Y10/00 , G11C7/00
摘要： Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.
摘要翻译：装置和方法可以包括用于晶闸管存储单元的写入方案，其中施加到晶闸管存储单元的栅极的访问脉冲相对于数据脉冲被调整以将数据写入晶闸管存储单元。一些写入方案可以显着地减少或消除未选择的数据线干扰。在各种实施例中，晶闸管存储单元可以由两个控制节点构成，其阴极或阳极耦合到存储器阵列中所有可控硅存储器单元公共的参考电压节点。公开了附加的装置和方法。

10. 发明授权

US08797794B2 Thyristor memory and methods of operation 有权
标题翻译：晶闸管记忆和操作方法
公开(公告)号：US08797794B2
公开(公告)日：2014-08-05
申请号：US13535048
申请日：2012-06-27
申请人： Rajesh N. Gupta
发明人： Rajesh N. Gupta
IPC分类号： G11C11/34 , G11C11/39 , B82Y10/00
CPC分类号： G11C11/39 , B82Y10/00 , G11C7/00
摘要： Apparatuses and methods can include write schemes for a thyristor memory cell in which an access pulse applied to the gate of the thyristor memory cell is adjusted relative to the data pulse to write data into the thyristor memory cell. Some of the write schemes may substantially reduce or eliminate an unselected data line disturb. In various embodiments, the thyristor memory cell can be structured with two control nodes and its cathode or anode coupled to a reference voltage node common to all thyristor memory cells in a memory array. Additional apparatuses and methods are disclosed.
摘要翻译：装置和方法可以包括用于晶闸管存储单元的写入方案，其中施加到晶闸管存储单元的栅极的访问脉冲相对于数据脉冲被调整以将数据写入晶闸管存储单元。一些写入方案可以显着地减少或消除未选择的数据线干扰。在各种实施例中，晶闸管存储单元可以由两个控制节点构成，其阴极或阳极耦合到存储器阵列中所有可控硅存储器单元公共的参考电压节点。公开了附加的装置和方法。

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