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51. 发明授权

US07599244B2 Semiconductor memory, memory controller and control method for semiconductor memory 有权
标题翻译：半导体存储器，存储器控制器和半导体存储器的控制方法
公开(公告)号：US07599244B2
公开(公告)日：2009-10-06
申请号：US11437719
申请日：2006-05-22
申请人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
发明人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
IPC分类号： G11C8/00
CPC分类号： G11C7/20 , G11C7/1072 , G11C7/22 , G11C7/225
摘要： A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.
摘要翻译：用于与时钟同步地输入和输出数据的半导体存储器包括用于接收时钟的时钟接收单元和用于在低功率待机之后最初接收与开启电源之后的时钟同步的第一特定命令的命令接收单元或者在初始化之后，接着开始命令接收。

52. 发明申请

US20080298159A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20080298159A1
公开(公告)日：2008-12-04
申请号：US12129433
申请日：2008-05-29
申请人： Kuninori Kawabata , Yoshiyuki Ishida , Satoshi Eto
发明人： Kuninori Kawabata , Yoshiyuki Ishida , Satoshi Eto
IPC分类号： G11C8/18
CPC分类号： G11C7/10
摘要： An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal output from the memory macro to a signal compliant with the system interface specification and outputs the same to the controller. By converting the system interface specification and the memory interface specification to each other by an interface conversion macro, a common memory macro can be mounted on a semiconductor integrated circuit even when the system interface specification differs. Accordingly, when designing a system, the design verification time, evaluation time, and test time of the semiconductor integrated circuit can be reduced. As a result, the design time and design cost of the semiconductor integrated circuit can be reduced.
摘要翻译：接口转换宏将符合从控制器输出的系统接口规范的信号转换为符合存储器接口规范的信号，并将其输出到存储器接口部分，并且还将从存储器宏输出的信号转换为信号符合系统接口规范，并将其输出到控制器。通过接口转换宏将系统接口规范和存储器接口规范相互转换，即使系统接口规范不同，公共存储器宏也可以安装在半导体集成电路上。因此，当设计系统时，可以减少半导体集成电路的设计验证时间，评估时间和测试时间。结果，可以减少半导体集成电路的设计时间和设计成本。

53. 发明授权

US07327627B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07327627B2
公开(公告)日：2008-02-05
申请号：US11452379
申请日：2006-06-14
申请人： Kuninori Kawabata , Shuzo Otsuka
发明人： Kuninori Kawabata , Shuzo Otsuka
IPC分类号： G11C7/00
CPC分类号： G11C11/40622 , G11C8/18 , G11C11/406
摘要： Out of memory blocks arranged in one direction, the memory blocks arranged at both ends are included in a partial area. Since part of control circuits operating the memory blocks arranged at the both ends are not shared by the other memory blocks, switching circuits connecting these control circuits to the memory blocks are constantly settable to an ON state. Since ON/OFF control of the switching circuits is not necessary, power consumption required for accessing the memory blocks arranged at the both ends is smaller than that required for accessing the other memory blocks. Therefore, including the memory blocks arranged at the both ends in a partial area makes it possible to reduce power consumption during a partial refresh mode (standby current).
摘要翻译：在一个方向上布置的存储器块不足，布置在两端的存储块被包括在部分区域中。由于设置在两端的存储块的一部分控制电路不被其他存储块共享，所以将这些控制电路连接到存储块的开关电路始终可设定为导通状态。由于不需要开关电路的ON / OFF控制，所以访问布置在两端的存储块所需的功耗小于访问其他存储块所需的功耗。因此，包括布置在部分区域的两端的存储块使得可以在部分刷新模式（待机电流）期间减少功耗。

54. 发明授权

US07212453B2 Semiconductor memory having an error correction function 有权
标题翻译：具有纠错功能的半导体存储器
公开(公告)号：US07212453B2
公开(公告)日：2007-05-01
申请号：US11155731
申请日：2005-06-20
申请人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
发明人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/1032 , G11C11/401 , G11C29/50016 , G11C29/52 , G11C2029/0409
摘要： Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.
摘要翻译：向/从外部端子输入/输出的常规数据被读取/写入常规单元阵列，并且从奇偶校验单元阵列读取/写入奇偶校验数据。由于奇偶校验数据由奇偶产生电路产生，因此难以将奇偶校验单元阵列所需的模式写入。常规数据和奇偶校验数据通过开关电路彼此交换，使得常规数据可以写入奇偶校验单元阵列，并且奇偶校验数据可以写入正常单元阵列。这使得能够将所需数据写入奇偶校验单元阵列。可以容易地进行奇偶校验数据的测试。特别地，可以容易地进行存储单元之间的泄漏测试等。

55. 发明申请

US20060221725A1 Semiconductor integrated circuit device 失效
公开(公告)号：US20060221725A1
公开(公告)日：2006-10-05
申请号：US11430935
申请日：2006-05-10
申请人： Kuninori Kawabata , Akira Kikutake , Shinichiro Shiratake
发明人： Kuninori Kawabata , Akira Kikutake , Shinichiro Shiratake
IPC分类号： G11C7/00
CPC分类号： G11C29/12 , G11C7/1048 , G11C11/4096
摘要： A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mode in which the signal lines are not precharged.

56. 发明申请

US20060156214A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060156214A1
公开(公告)日：2006-07-13
申请号：US11092704
申请日：2005-03-30
申请人： Akira Kikutake , Kuninori Kawabata
发明人： Akira Kikutake , Kuninori Kawabata
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/1032
摘要： Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.
摘要翻译：在奇偶校验单元阵列的两侧设置有第一规则单元阵列及其子奇偶校验生成电路，以及第二正则单元阵列和副奇偶校验生成电路。子校验生成电路根据从第一和第二规则单元阵列同时读出的读取数据生成子奇偶校验数据。主奇偶生成电路根据子校验数据奇偶校验数据与常规单元阵列共同生成，不以分布式布置，而是对应于奇偶校验单元阵列布置。因此，可以防止半导体存储器的布局设计，布局验证等复杂化。结果，可以最佳地布置奇偶产生电路，减少开发时间，并且可以减少半导体存储器的缺陷分析时间。

57. 发明申请

US20060156212A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060156212A1
公开(公告)日：2006-07-13
申请号：US11092715
申请日：2005-03-30
申请人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata
发明人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G11C29/42 , G11C11/401 , G11C29/10
摘要： A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, and thus writes test data into a regular memory cell at a location corresponding to a location of a parity memory cell into which test parity data are written in each of regular cell arrays. Therefore, since a common test pattern can be used to test both the regular memory cell and the parity memory cell, test cost can be curtailed.
摘要翻译：普通写入数据选择电路在正常工作模式下工作，从而将通过外部数据终端接收的数据输出到根据地址选择的任何一个常规单元阵列。测试写入控制电路在测试模式下操作，并且因此将测试数据写入与校验奇偶校验数据写入每个常规单元阵列中的奇偶校验存储单元的位置相对应的位置处的常规存储单元。因此，由于可以使用公共测试模式来测试常规存储单元和奇偶校验存储单元，所以可以减少测试成本。

58. 发明授权

US06628564B1 Semiconductor memory device capable of driving non-selected word lines to first and second potentials 有权
标题翻译：能够将未选择的字线驱动到第一和第二电位的半导体存储器件
公开(公告)号：US06628564B1
公开(公告)日：2003-09-30
申请号：US09339855
申请日：1999-06-25
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C808
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.
摘要翻译：半导体器件包括字线驱动电路，通过驱动连接到存储单元的字线并在字线的复位操作时切换字线驱动电路的复位电平来重置字线。此外，半导体器件包括通过布置多个存储单元形成的存储单元阵列和用于选择第一电位或第二电位的复位电平开关电路，并将第一电位或第二电位提供给字线驱动电路。

59. 发明授权

US06605963B2 Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中半导体集成电路和晶体管的源极电位切换方法
公开(公告)号：US06605963B2
公开(公告)日：2003-08-12
申请号：US09412590
申请日：1999-10-05
申请人： Ayako Kitamoto , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Hideki Kanou , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Ayako Kitamoto , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Hideki Kanou , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： H03K19185
CPC分类号： H03K19/0013 , H03K3/356113 , H03K17/102 , H03K19/00361 , H03K2217/0036
摘要： A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.
摘要翻译：公开了一种半导体集成电路，其包括具有预定功能的电路单元，例如通过多个晶体管的组合的电平移位器电路或驱动晶体管电路。在电路单元的多个晶体管中，改变了在电路单元的待机期间适于关断的至少一个晶体管的源极电位。优选地，半导体集成电路被配置为减少在电路单元的待机时段期间流过至少一个晶体管的源极和漏极之间的亚阈值电流，其在基于以使得在晶体管的栅极和源极之间施加预定的偏置电压的方式使电路单元的待机时段。还公开了一种在具有上述结构的半导体集成电路中切换至少一个晶体管的源极电位的方法。

60. 发明授权

US06522003B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06522003B1
公开(公告)日：2003-02-18
申请号：US09472833
申请日：1999-12-28
申请人： Takayoshi Minami , Osamu Tsuboi , Toshimi Ikeda , Masato Matsumiya , Kuninori Kawabata
发明人： Takayoshi Minami , Osamu Tsuboi , Toshimi Ikeda , Masato Matsumiya , Kuninori Kawabata
IPC分类号： H01L2348
CPC分类号： G03F7/70633 , G03F9/7084 , H01L23/522 , H01L23/544 , H01L27/10882 , H01L27/10897 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device characterized by comprising a first insulating film formed on the semiconductor substrate, a first wiring or mark formed on the first insulating film, an electrically isolated pattern formed under the first insulating film and below the first wiring or mark, a hole formed in the first insulating film to connect the first wiring or mark and the electrically isolated pattern, and a second insulating film for covering the first wiring or mark.
摘要翻译：一种半导体器件，其特征在于，包括形成在所述半导体衬底上的第一绝缘膜，形成在所述第一绝缘膜上的第一布线或标记，形成在所述第一绝缘膜下方且在所述第一布线或标记下方的电隔离图案，用于连接第一布线或标记和电隔离图案的第一绝缘膜，以及用于覆盖第一布线或标记的第二绝缘膜。

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