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1. 发明申请

US20060098523A1 Semiconductor memory device capable of driving non-selected word lines to first and second potentials 失效
标题翻译：能够将未选择的字线驱动到第一和第二电位的半导体存储器件
公开(公告)号：US20060098523A1
公开(公告)日：2006-05-11
申请号：US11313963
申请日：2005-12-22
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.
摘要翻译：半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量存储单元阵列。此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

2. 发明申请

US20100220540A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS 审中-公开
公开(公告)号：US20100220540A1
公开(公告)日：2010-09-02
申请号：US12718808
申请日：2010-03-05
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

3. 发明授权

US07706209B2 Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation 失效
标题翻译：能够基于银行存取操作将未选字线驱动到可变负电位的半导体存储器件
公开(公告)号：US07706209B2
公开(公告)日：2010-04-27
申请号：US11313963
申请日：2005-12-22
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C8/08
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device, including a word line driver for driving a word line connected to a memory cell in a memory cell array and for resetting the word line when the memory cell changes from an activated to a standby state. The reset level of the word line driver is set when resetting of the word line is performed, and may be switched between first and second potentials. A word line reset level generating circuit varies the amount of negative potential current supply in accordance with memory cell array operating conditions. The semiconductor device includes a plurality of power source circuits, each having an oscillation circuit and a capacitor, for driving the capacitor via an oscillation signal outputted by the oscillation circuit. At least some power source circuits share a common oscillation circuit, and different capacitors are driven via the common oscillation signal.
摘要翻译：一种半导体器件，包括用于驱动连接到存储单元阵列中的存储单元的字线的字线驱动器，以及当存储器单元从激活状态变为待机状态时重新设定字线。当执行字线的复位时，字线驱动器的复位电平被设置，并且可以在第一和第二电位之间切换。字线复位电平发生电路根据存储单元阵列工作条件改变负电位电流供给量。半导体器件包括多个电源电路，每个电源电路具有振荡电路和电容器，用于经由振荡电路输出的振荡信号来驱动电容器。至少一些电源电路共用一个共同的振荡电路，而不同的电容通过公共振荡信号驱动。

4. 发明授权

US06628564B1 Semiconductor memory device capable of driving non-selected word lines to first and second potentials 有权
标题翻译：能够将未选择的字线驱动到第一和第二电位的半导体存储器件
公开(公告)号：US06628564B1
公开(公告)日：2003-09-30
申请号：US09339855
申请日：1999-06-25
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C808
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit resetting the word line by driving the word line connected to a memory cell and switching a reset level of the word line drive circuit at the time of the reset operation of the word line. Further, a semiconductor device includes a memory cell array formed by arranging a plurality of memory cells and a reset level switch circuit for selecting a first potential or a second potential and supplying the first potential or the second potential to the word line drive circuit.
摘要翻译：半导体器件包括字线驱动电路，通过驱动连接到存储单元的字线并在字线的复位操作时切换字线驱动电路的复位电平来重置字线。此外，半导体器件包括通过布置多个存储单元形成的存储单元阵列和用于选择第一电位或第二电位的复位电平开关电路，并将第一电位或第二电位提供给字线驱动电路。

5. 发明申请

US20100321983A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS 审中-公开
标题翻译：能够驱动非选定字线的第一和第二电位的半导体存储器件
公开(公告)号：US20100321983A1
公开(公告)日：2010-12-23
申请号：US12718819
申请日：2010-03-05
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C11/24 , G11C5/14
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.
摘要翻译：半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量存储单元阵列。此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

6. 发明授权

US07079443B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07079443B2
公开(公告)日：2006-07-18
申请号：US10631752
申请日：2003-08-01
申请人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
发明人： Masato Takita , Masato Matsumiya , Satoshi Eto , Toshikazu Nakamura , Masatomo Hasegawa , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Toru Koga , Yuki Ishii , Shinichi Yamada , Kaoru Mori
IPC分类号： G11C8/08
CPC分类号： G11C5/147 , G11C8/08 , G11C8/12 , G11C11/4074 , G11C11/4085 , G11C2207/2227
摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.
摘要翻译：半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量存储单元阵列。此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

7. 发明授权

US6147919A Semiconductor memory employing direct-type sense amplifiers capable of realizing high-speed access 有权
标题翻译：采用直接式读出放大器的半导体存储器，能够实现高速存取
公开(公告)号：US6147919A
公开(公告)日：2000-11-14
申请号：US274245
申请日：1999-03-23
申请人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Masatomo Hasegawa , Hideki Kanou , Ayako Kitamoto , Toru Koga , Yuki Ishii , Akira Kikutake , Yuichi Uzawa
发明人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Masatomo Hasegawa , Hideki Kanou , Ayako Kitamoto , Toru Koga , Yuki Ishii , Akira Kikutake , Yuichi Uzawa
IPC分类号： H01L27/10 , G11C7/06 , G11C7/12 , G11C7/02
CPC分类号： G11C7/06 , G11C7/12
摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.
摘要翻译：半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。读出放大器在每行中分组成读出放大器模块。只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器。本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。只写列选择线由用于控制读出放大器的信号控制。

8. 发明授权

US06605963B2 Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit 有权
标题翻译：半导体集成电路中半导体集成电路和晶体管的源极电位切换方法
公开(公告)号：US06605963B2
公开(公告)日：2003-08-12
申请号：US09412590
申请日：1999-10-05
申请人： Ayako Kitamoto , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Hideki Kanou , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Ayako Kitamoto , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Hideki Kanou , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： H03K19185
CPC分类号： H03K19/0013 , H03K3/356113 , H03K17/102 , H03K19/00361 , H03K2217/0036
摘要： A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.
摘要翻译：公开了一种半导体集成电路，其包括具有预定功能的电路单元，例如通过多个晶体管的组合的电平移位器电路或驱动晶体管电路。在电路单元的多个晶体管中，改变了在电路单元的待机期间适于关断的至少一个晶体管的源极电位。优选地，半导体集成电路被配置为减少在电路单元的待机时段期间流过至少一个晶体管的源极和漏极之间的亚阈值电流，其在基于以使得在晶体管的栅极和源极之间施加预定的偏置电压的方式使电路单元的待机时段。还公开了一种在具有上述结构的半导体集成电路中切换至少一个晶体管的源极电位的方法。

9. 发明授权

US06172537B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06172537B2
公开(公告)日：2001-01-09
申请号：US09286439
申请日：1999-04-06
申请人： Hideki Kanou , Masato Matsumiya , Satoshi Eto , Masato Takita , Ayako Kitamoto , Toshikazu Nakamura , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Hideki Kanou , Masato Matsumiya , Satoshi Eto , Masato Takita , Ayako Kitamoto , Toshikazu Nakamura , Kuninori Kawabata , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： H03K1700
CPC分类号： G11C7/106 , G06F1/10 , G11C7/1051 , G11C7/1069 , G11C7/22 , G11C7/222 , H03K5/131 , H03K5/133 , H03L7/0814
摘要： A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.
摘要翻译：半导体器件具有用于调整外部时钟的相位的DLL电路等，并且产生在给定相位之后滞后的内部时钟。半导体器件还包括时钟频率判定单元，用于根据指示DLL电路等中的第一时钟的延迟值的指示信号等来判定第一时钟的频率，以输出控制信号; 以及时钟选择单元，用于响应于控制信号选择第一时钟和第二时钟中的任一个。

10. 发明授权

US6072749A Memory device preventing a slow operation through a mask signal 有权
标题翻译：存储器件通过掩码信号防止慢读取操作
公开(公告)号：US6072749A
公开(公告)日：2000-06-06
申请号：US166070
申请日：1998-10-05
申请人： Toshikazu Nakamura , Masato Matsumiya , Satoshi Eto , Masato Takita , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
发明人： Toshikazu Nakamura , Masato Matsumiya , Satoshi Eto , Masato Takita , Ayako Kitamoto , Kuninori Kawabata , Hideki Kanou , Masatomo Hasegawa , Toru Koga , Yuki Ishii
IPC分类号： G11C16/02 , G11C7/10 , G11C11/407 , G11C11/409 , G11C16/06 , G11C8/00
CPC分类号： G11C7/1018
摘要： This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.
摘要翻译：本发明是具有这样的结构的存储器件，该结构使用从时钟CLK到用于产生列选择信号CL的预解码器和列解码器的关键路径内的I / O掩码信号DQM消除了逻辑电路。消除了用于产生列选择信号的关键路径内使用I / O掩码信号DQM的逻辑电路，并且从提供时钟直到产生列选择信号的时间尽可能地缩短。另一方面，为了在突发写入模式期间使I / O掩模成为可能，基于I / O掩码信号DQM执行写入放大器的驱动控制。具体地，响应于I / O掩码信号DQM，禁止或允许写入放大器的激活。

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