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1. 发明申请

US20070180202A1 Memory controller, semiconductor memory, and memory system 有权
标题翻译：存储器控制器，半导体存储器和存储器系统
公开(公告)号：US20070180202A1
公开(公告)日：2007-08-02
申请号：US11442576
申请日：2006-05-30
申请人： Kuninori Kawabata , Satoshi Eto , Toshiya Miyo
发明人： Kuninori Kawabata , Satoshi Eto , Toshiya Miyo
IPC分类号： G06F13/00
CPC分类号： G06F13/1694 , G06F12/02
摘要： A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.
摘要翻译：连接到存储器的存储器控制器包括：地址接收单元，用于接收与命令一起外部输入的地址码; 以及命令转换单元，用于当与第一命令一起输入的地址代码指定未实现存储器的地址空间时，向存储器输出用于基于地址代码改变存储器的内部设置的MRS命令。

2. 发明授权

US08001450B2 Semiconductor memory device capable of changing ECC code length 有权
标题翻译：能够改变ECC码长度的半导体存储器件
公开(公告)号：US08001450B2
公开(公告)日：2011-08-16
申请号：US11878867
申请日：2007-07-27
申请人： Yasuhiro Onishi , Toshiya Miyo
发明人： Yasuhiro Onishi , Toshiya Miyo
IPC分类号： H03M13/00
CPC分类号： G06F11/1048
摘要： The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
摘要翻译：存储单元阵列中的数据存储单元阵列和奇偶校验存储单元阵列具有能够对应于多个ECC码长度的结构。从写入数据产生奇偶校验的输入侧奇偶校验生成电路，从读取数据生成奇偶校验的输出侧奇偶校验生成电路，以及从读出的奇偶校验位生成表示错误位的校正子位的校正子生成电路，奇偶校验位构成为能够根据多个ECC码长度进行切换。

3. 发明申请

US20080034270A1 Semiconductor memory device capable of changing ECC code length 有权
标题翻译：能够改变ECC码长度的半导体存储器件
公开(公告)号：US20080034270A1
公开(公告)日：2008-02-07
申请号：US11878867
申请日：2007-07-27
申请人： Yasuhiro Onishi , Toshiya Miyo
发明人： Yasuhiro Onishi , Toshiya Miyo
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
摘要翻译：存储单元阵列中的数据存储单元阵列和奇偶校验存储单元阵列具有能够对应于多个ECC码长度的结构。从写入数据产生奇偶校验的输入侧奇偶校验生成电路，从读取数据生成奇偶校验的输出侧奇偶校验生成电路，以及从读出的奇偶校验位生成表示错误位的校正子位的校正子生成电路，奇偶校验位构成为能够根据多个ECC码长度进行切换。

4. 发明授权

US07072243B2 Semiconductor memory 失效
公开(公告)号：US07072243B2
公开(公告)日：2006-07-04
申请号：US10965951
申请日：2004-10-18
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C8/00
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

5. 发明授权

US07064998B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US07064998B2
公开(公告)日：2006-06-20
申请号：US11215045
申请日：2005-08-31
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.
摘要翻译：定时器从接收外部接入信号测量预定时间，并且在经过预定时间之后输出接入请求信号。外部访问信号使存储器核心执行读取操作，并且访问请求信号使得存储器核心操作。预定时间被设定为比存储器芯执行单次操作的核心操作时间长。因此，当外部访问信号在比预定时间短的时间内变化时，存储器核不执行操作。因此，即使当存储器核心不能正常操作的间隔提供外部访问信号时，也可以防止存储器芯故障并保留其中的数据崩溃。

6. 发明授权

US08264869B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US08264869B2
公开(公告)日：2012-09-11
申请号：US12779707
申请日：2010-05-13
申请人： Toshiya Miyo , Atsumasa Sako
发明人： Toshiya Miyo , Atsumasa Sako
IPC分类号： G11C11/24
CPC分类号： G11C5/145 , G11C8/18 , G11C11/4074
摘要： A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the plate line to a first power supply line when an access to the memory cell array is caused.
摘要翻译：一种半导体存储装置，包括配置有包括MOS电容器的存储单元的存储单元阵列; 电源单元，其将板电压提供给耦合到所述MOS电容器的栅电极的板线; 以及当引起对存储单元阵列的访问时将板线耦合到第一电源线的开关。

7. 发明申请

US20100290267A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20100290267A1
公开(公告)日：2010-11-18
申请号：US12779707
申请日：2010-05-13
申请人： Toshiya MIYO , Atsumasa SAKO
发明人： Toshiya MIYO , Atsumasa SAKO
IPC分类号： G11C11/24 , G11C5/14
CPC分类号： G11C5/145 , G11C8/18 , G11C11/4074
摘要： A semiconductor storage device includes a memory cell array in which a memory cell including an MOS capacitor is arranged; a power supply unit that supplies a plate voltage to a plate line that is coupled to a gate electrode of the MOS capacitor; and a switch that couples the plate line to a first power supply line when an access to the memory cell array is caused.
摘要翻译：一种半导体存储装置，包括配置有包括MOS电容器的存储单元的存储单元阵列; 电源单元，其将板电压提供给耦合到所述MOS电容器的栅电极的板线; 以及当引起对存储单元阵列的访问时将板线耦合到第一电源线的开关。

8. 发明申请

US20070177449A1 Semiconductor memory, memory controller and control method for semiconductor memory 有权
标题翻译：半导体存储器，存储器控制器和半导体存储器的控制方法
公开(公告)号：US20070177449A1
公开(公告)日：2007-08-02
申请号：US11437719
申请日：2006-05-22
申请人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
发明人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
IPC分类号： G11C8/00
CPC分类号： G11C7/20 , G11C7/1072 , G11C7/22 , G11C7/225
摘要： Semiconductor memory for inputting and outputting data synchronously with a clock, comprising: a clock reception unit for receiving the clock; and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.
摘要翻译：用于与时钟同步输入和输出数据的半导体存储器，包括：用于接收时钟的时钟接收单元; 以及命令接收单元，用于在低功率待机或初始化之后，首先接收与开启电源之后的时钟同步的第一特定命令，然后开始命令接收。

9. 发明授权

US07193922B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07193922B2
公开(公告)日：2007-03-20
申请号：US10968072
申请日：2004-10-20
申请人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
发明人： Toshiya Miyo , Toshikazu Nakamura , Satoshi Eto
IPC分类号： G11C8/00 , G11C5/06
CPC分类号： G11C11/4097
摘要： Second memory cells of a second memory block each have an area 2a times (a is a positive integer) that of each first memory cell of a first memory block. Sizing the first and second memory cells in a predetermined ratio can make easily identical the dimensions of the first memory block and the second memory block. Consequently, it is possible to easily align peripheral circuits to lie around the plurality of first and second memory blocks, such as decoders. This also facilitates the wiring of signal lines to be connected to the peripheral circuits. This makes it possible to improve the layout design efficiency for a semiconductor integrated circuit. Thus, a plurality of types of memory blocks can be formed on a semiconductor integrated circuit efficiently. The semiconductor integrated circuit can be prevented from increasing in chip size depending on the layout design, owing to its simplified layout.
摘要翻译：第二存储器块的第二存储单元分别具有第一存储器块的每个第一存储器单元的区域2（a）为正整数）。以预定比例对第一和第二存储器单元进行尺寸可以使得第一存储块和第二存储块的尺寸容易相同。因此，可以容易地将外围电路对准在诸如解码器之类的多个第一和第二存储器块周围。这也有助于连接到外围电路的信号线的布线。这使得可以提高半导体集成电路的布局设计效率。因此，可以有效地在半导体集成电路上形成多种类型的存储块。由于布局简单，可以防止半导体集成电路因布局设计而增加芯片尺寸。

10. 发明申请

US20060023547A1 Semiconductor memory 失效
公开(公告)号：US20060023547A1
公开(公告)日：2006-02-02
申请号：US11215045
申请日：2005-08-31
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

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