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1. 发明授权

US07599244B2 Semiconductor memory, memory controller and control method for semiconductor memory 有权
标题翻译：半导体存储器，存储器控制器和半导体存储器的控制方法
公开(公告)号：US07599244B2
公开(公告)日：2009-10-06
申请号：US11437719
申请日：2006-05-22
申请人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
发明人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
IPC分类号： G11C8/00
CPC分类号： G11C7/20 , G11C7/1072 , G11C7/22 , G11C7/225
摘要： A semiconductor memory for inputting and outputting data synchronously with a clock includes a clock reception unit for receiving the clock, and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.
摘要翻译：用于与时钟同步地输入和输出数据的半导体存储器包括用于接收时钟的时钟接收单元和用于在低功率待机之后最初接收与开启电源之后的时钟同步的第一特定命令的命令接收单元或者在初始化之后，接着开始命令接收。

2. 发明申请

US20070177449A1 Semiconductor memory, memory controller and control method for semiconductor memory 有权
标题翻译：半导体存储器，存储器控制器和半导体存储器的控制方法
公开(公告)号：US20070177449A1
公开(公告)日：2007-08-02
申请号：US11437719
申请日：2006-05-22
申请人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
发明人： Satoshi Eto , Kuninori Kawabata , Toshiya Miyo , Yuji Serizawa
IPC分类号： G11C8/00
CPC分类号： G11C7/20 , G11C7/1072 , G11C7/22 , G11C7/225
摘要： Semiconductor memory for inputting and outputting data synchronously with a clock, comprising: a clock reception unit for receiving the clock; and a command reception unit for initially receiving a first specific command synchronizing with the clock after turning a power on, after a low-power standby or after an initialization, followed by starting a command reception.
摘要翻译：用于与时钟同步输入和输出数据的半导体存储器，包括：用于接收时钟的时钟接收单元; 以及命令接收单元，用于在低功率待机或初始化之后，首先接收与开启电源之后的时钟同步的第一特定命令，然后开始命令接收。

3. 发明申请

US20070180202A1 Memory controller, semiconductor memory, and memory system 有权
标题翻译：存储器控制器，半导体存储器和存储器系统
公开(公告)号：US20070180202A1
公开(公告)日：2007-08-02
申请号：US11442576
申请日：2006-05-30
申请人： Kuninori Kawabata , Satoshi Eto , Toshiya Miyo
发明人： Kuninori Kawabata , Satoshi Eto , Toshiya Miyo
IPC分类号： G06F13/00
CPC分类号： G06F13/1694 , G06F12/02
摘要： A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.
摘要翻译：连接到存储器的存储器控制器包括：地址接收单元，用于接收与命令一起外部输入的地址码; 以及命令转换单元，用于当与第一命令一起输入的地址代码指定未实现存储器的地址空间时，向存储器输出用于基于地址代码改变存储器的内部设置的MRS命令。

4. 发明授权

US07818516B2 Memory controller, semiconductor memory, and memory system 有权
标题翻译：存储器控制器，半导体存储器和存储器系统
公开(公告)号：US07818516B2
公开(公告)日：2010-10-19
申请号：US11442576
申请日：2006-05-30
申请人： Kuninori Kawabata , Satoshi Eto , Toshiya Miyo
发明人： Kuninori Kawabata , Satoshi Eto , Toshiya Miyo
IPC分类号： G06F13/00
CPC分类号： G06F13/1694 , G06F12/02
摘要： A memory controller connected to memory includes: an address reception unit for receiving an address code externally input together with a command; and a command conversion unit for outputting to the memory an MRS command to change the internal settings of the memory based on the address code when the address code input together with a first command specifies an address space for which the memory is not implemented.
摘要翻译：连接到存储器的存储器控制器包括：地址接收单元，用于接收与命令一起外部输入的地址码; 以及命令转换单元，用于当与第一命令一起输入的地址代码指定未实现存储器的地址空间时，向存储器输出用于基于地址代码改变存储器的内部设置的MRS命令。

5. 发明申请

US20060133166A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060133166A1
公开(公告)日：2006-06-22
申请号：US11155731
申请日：2005-06-20
申请人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
发明人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/1032 , G11C11/401 , G11C29/50016 , G11C29/52 , G11C2029/0409
摘要： Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.
摘要翻译：向/从外部端子输入/输出的常规数据被读取/写入常规单元阵列，并且从奇偶校验单元阵列读取/写入奇偶校验数据。由于奇偶校验数据由奇偶产生电路产生，因此难以将奇偶校验单元阵列所需的模式写入。常规数据和奇偶校验数据通过开关电路彼此交换，使得常规数据可以写入奇偶校验单元阵列，并且奇偶校验数据可以写入正常单元阵列。这使得能够将所需数据写入奇偶校验单元阵列。可以容易地进行奇偶校验数据的测试。特别地，可以容易地进行存储单元之间的泄漏测试等。

6. 发明授权

US07212453B2 Semiconductor memory having an error correction function 有权
标题翻译：具有纠错功能的半导体存储器
公开(公告)号：US07212453B2
公开(公告)日：2007-05-01
申请号：US11155731
申请日：2005-06-20
申请人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
发明人： Akira Kikutake , Yasuhiro Onishi , Kuninori Kawabata , Junichi Sasaki , Toshiya Miyo
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G06F11/1032 , G11C11/401 , G11C29/50016 , G11C29/52 , G11C2029/0409
摘要： Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.
摘要翻译：向/从外部端子输入/输出的常规数据被读取/写入常规单元阵列，并且从奇偶校验单元阵列读取/写入奇偶校验数据。由于奇偶校验数据由奇偶产生电路产生，因此难以将奇偶校验单元阵列所需的模式写入。常规数据和奇偶校验数据通过开关电路彼此交换，使得常规数据可以写入奇偶校验单元阵列，并且奇偶校验数据可以写入正常单元阵列。这使得能够将所需数据写入奇偶校验单元阵列。可以容易地进行奇偶校验数据的测试。特别地，可以容易地进行存储单元之间的泄漏测试等。

7. 发明授权

US07072243B2 Semiconductor memory 失效
公开(公告)号：US07072243B2
公开(公告)日：2006-07-04
申请号：US10965951
申请日：2004-10-18
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C8/00
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.

8. 发明授权

US07064998B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US07064998B2
公开(公告)日：2006-06-20
申请号：US11215045
申请日：2005-08-31
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.
摘要翻译：定时器从接收外部接入信号测量预定时间，并且在经过预定时间之后输出接入请求信号。外部访问信号使存储器核心执行读取操作，并且访问请求信号使得存储器核心操作。预定时间被设定为比存储器芯执行单次操作的核心操作时间长。因此，当外部访问信号在比预定时间短的时间内变化时，存储器核不执行操作。因此，即使当存储器核心不能正常操作的间隔提供外部访问信号时，也可以防止存储器芯故障并保留其中的数据崩溃。

9. 发明授权

US06925027B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06925027B2
公开(公告)日：2005-08-02
申请号：US10698450
申请日：2003-11-03
申请人： Satoshi Eto , Toshikazu Nakamura , Toshiya Miyo
发明人： Satoshi Eto , Toshikazu Nakamura , Toshiya Miyo
IPC分类号： G11C11/403 , G11C7/22 , G11C11/406 , G11C11/4076 , G11C11/4193 , G11C7/00
CPC分类号： G11C7/22 , G11C11/406 , G11C11/4076 , G11C2207/2227 , G11C2211/4067
摘要： A semiconductor memory with a memory core for dynamically holding data in which a data collision at the time of the semiconductor memory making the transition from a standby state to a nonstandby state is prevented. A first buffer circuit inputs an enable signal for controlling a standby state or a nonstandby state. A second buffer circuit outputs a predetermined logic signal or a read/write signal for controlling the reading of data from or the writing of data to the memory core in accordance with the enable signal. A third buffer circuit outputs an inverted signal obtained by inverting the logic signal or the read/write signal in accordance with the enable signal. A control circuit controls the reading or writing of the data by the read/write signal outputted from the second buffer circuit. A data output control circuit controls the inputting of the data from or the outputting of the data to the outside by the inverted signal or the read/write signal outputted from the third buffer circuit.
摘要翻译：一种具有用于动态保持数据的存储器的半导体存储器，其中半导体存储器从待机状态转换到非状态时的数据冲突被防止。第一缓冲电路输入用于控制待机状态或非状态的使能信号。第二缓冲电路根据使能信号输出预定的逻辑信号或读/写信号，用于控制数据的读取或向数据的写入。第三缓冲电路根据使能信号输出通过反相逻辑信号或读/写信号而获得的反相信号。控制电路通过从第二缓冲电路输出的读/写信号来控制数据的读取或写入。数据输出控制电路通过从第三缓冲电路输出的反相信号或读/写信号来控制数据的输入或输出到外部。

10. 发明申请

US20050052941A1 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US20050052941A1
公开(公告)日：2005-03-10
申请号：US10965951
申请日：2004-10-18
申请人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
发明人： Toshikazu Nakamura , Satoshi Eto , Toshiya Miyo
IPC分类号： G11C7/22 , G11C11/406 , G11C11/4076 , G11C8/02
CPC分类号： G11C11/40603 , G11C7/22 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/2281 , G11C2211/4061
摘要： A timer measures a predetermined time from the reception of an external access signal, and outputs an access request signal after the predetermined time has elapsed. The external access signal causes a memory core to execute a read operation, and the access request signal causes the memory core to operate. The predetermined time is set to be longer than a core operation time for the memory core to perform a single operation. The memory core thus performs no operation when the external access signal varies in a time shorter than the predetermined time. Consequently, it is possible to prevent the memory core from malfunctioning and data retained therein from crashing even when external access signals are supplied at intervals at which the memory core is unable to properly operate.
摘要翻译：定时器从接收外部接入信号测量预定时间，并且在经过预定时间之后输出接入请求信号。外部访问信号使存储器核心执行读取操作，并且访问请求信号使得存储器核心操作。预定时间被设定为比存储器芯执行单次操作的核心操作时间长。因此，当外部访问信号在比预定时间短的时间内变化时，存储器核不执行操作。因此，即使当存储器核心不能正常操作的间隔提供外部访问信号时，也可以防止存储器芯故障并保留其中的数据崩溃。

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