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51. 发明授权

US06274499B1 Method to avoid copper contamination during copper etching and CMP 有权
标题翻译：在铜蚀刻和CMP期间避免铜污染的方法
公开(公告)号：US06274499B1
公开(公告)日：2001-08-14
申请号：US09442493
申请日：1999-11-19
申请人： Subhash Gupta , Paul Kwok Keung Ho , Mei Sheng Zhou , Ramasamy Chockalingam
发明人： Subhash Gupta , Paul Kwok Keung Ho , Mei Sheng Zhou , Ramasamy Chockalingam
IPC分类号： H01L21302
CPC分类号： H01L21/76801 , H01L21/3212 , H01L21/32134 , H01L21/76807 , H01L21/76834
摘要： In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A copper layer is deposited overlying a barrier metal layer over the dielectric cap layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening where the dielectric cap layer prevents copper contamination of the dielectric layer during polishing and cleaning.
摘要翻译：根据本发明的目的，描述了通过形成用于隔离下面介电层的电介质盖，在蚀刻，CMP或后蚀刻和后CMP清洗中防止金属间电介质层的铜污染的新方法。在本发明的一个实施例中，提供覆盖在半导体衬底上的电介质层。介电覆盖层沉积在介电层上。通孔被图案化并填充有金属层并且被平坦化。沉积在平坦化的金属层和电介质盖层上的铜层。铜层被蚀刻以形成铜线，其中电介质盖层在蚀刻和清洁期间防止电介质层的铜污染。在本发明的另一个实施例中，提供覆盖半导体衬底的电介质层。介电覆盖层沉积在介电层上。通过电介质盖层和电介质层形成双镶嵌开口。将铜层沉积在电介质盖层上方的阻挡金属层上，并填充双镶嵌开口。将铜层抛光回来，仅在双镶嵌开口中留下铜层，其中介电盖层在抛光和清洁期间防止电介质层的铜污染。

52. 发明授权

US06251786B1 Method to create a copper dual damascene structure with less dishing and erosion 有权
标题翻译：创建铜双镶嵌结构的方法，具有较少的凹陷和侵蚀
公开(公告)号：US06251786B1
公开(公告)日：2001-06-26
申请号：US09390783
申请日：1999-09-07
申请人： Mei Sheng Zhou , Paul Kwok Keung Ho , Subhash Gupta
发明人： Mei Sheng Zhou , Paul Kwok Keung Ho , Subhash Gupta
IPC分类号： H01L2100
CPC分类号： H01L21/76834 , H01L21/3212 , H01L21/76807 , H01L21/7684 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.
摘要翻译：在电介质层中产生双镶嵌结构，该结构包含阻挡层，而覆盖层可以设置在电介质层上，也可以不设置在电介质层上，以进一步保护双镶嵌结构。双镶嵌结构中的铜的表面是凹进的，通过CMP或等离子体蚀刻沉积并平面化/部分去除薄膜，从而在双镶嵌结构的铜上方提供坚固的表面，防止该镶嵌结构的凹陷和侵蚀表面。

53. 发明授权

US06225202B1 Selective etching of unreacted nickel after salicidation 有权
标题翻译：腐蚀后对未反应的镍进行选择性蚀刻
公开(公告)号：US06225202B1
公开(公告)日：2001-05-01
申请号：US09598689
申请日：2000-06-21
申请人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
发明人： Subhash Gupta , Mei-Sheng Zhou , Simon Chooi , Sangki Hong
IPC分类号： H01L214763
CPC分类号： H01L29/665 , C23F4/00 , H01L21/32136
摘要： A method for removing unreacted nickel or cobalt after silicidation using carbon monoxide dry stripping is described. Shallow trench isolation regions are formed in a semiconductor substrate surrounding and electrically isolating an active area from other active areas. A gate electrode and associated source and drain regions are formed in the active area wherein dielectric spacers are formed on sidewalls of the gate electrode. A nickel or cobalt layer is deposited over the gate electrode and associated source and drain regions, shallow trench isolation regions, and dielectric spacers. The semiconductor substrate is annealed whereby the nickel or cobalt layer overlying the gate electrode and said source and drain regions is transformed into a nickel or cobalt silicide layer and wherein the nickel or cobalt layer overlying the dielectric spacers and the shallow trench isolation regions is unreacted. The unreacted nickel or cobalt layer is exposed to a plasma containing carbon monoxide gas wherein the carbon monoxide gas reacts with the unreacted nickel or cobalt thereby removing the unreacted nickel or cobalt from the substrate to complete salicidation of the integrated circuit device.
摘要翻译：描述了使用一氧化碳干燥汽提在硅化后除去未反应的镍或钴的方法。在半导体衬底中形成浅沟槽隔离区域，该半导体衬底围绕并使活性区域与其它有源区域电隔离。在有源区域中形成栅电极和相关源极和漏极区，其中在栅电极的侧壁上形成有电介质间隔物。在栅极电极和相关的源极和漏极区域，浅沟槽隔离区域和介电间隔物上沉积镍或钴层。半导体衬底被退火，由此将覆盖在栅电极和所述源极和漏极区域上的镍或钴层转变成镍或钴硅化物层，并且其中覆盖电介质间隔物和浅沟槽隔离区的镍或钴层是未反应的。将未反应的镍或钴层暴露于含有一氧化碳气体的等离子体中，其中一氧化碳气体与未反应的镍或钴反应，从而从基板除去未反应的镍或钴，以完成集成电路器件的水化。

54. 发明授权

US06184138B2 Method to create a controllable and reproducible dual copper damascene structure 有权
标题翻译：创建可控和可重复的双铜镶嵌结构的方法
公开(公告)号：US06184138B2
公开(公告)日：2001-02-06
申请号：US09390782
申请日：1999-09-07
申请人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta
发明人： Paul Kwok Keung Ho , Mei Sheng Zhou , Subhash Gupta
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76874 , H01L21/76876 , H01L21/76877 , H01L21/76879
摘要： A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is blanket deposited, a copper seed layer is deposited over the barrier layer. The dual damascene structure is then filled with a spin-on material. The barrier layer and the copper seed layer are removed above the cap layer; the cap layer can be partially removed or can be left in place. The spin on material remains in place in the via and trench opening during the operation of removing the copper seed layer and the barrier layer from above the cap surface thereby protecting the inside surfaces of these openings. The spin-on material is next removed from the dual damascene structure and copper is deposited. The cap layer that is still present above the surface of the IMD protects the dielectric from being contaminated with copper solution during the deposition of the copper. The excess copper is removed using a touch-up CMP. The cap layer over the surface of the IMD can, after the copper has been deposited, be removed if this is so desired. As a final step in the process, a liner or oxidation/diffusion protection layer is deposited over the dual damascene structure and its surrounding area.
摘要翻译：提供了一种构建铜双镶嵌结构的新方法。一层IMD沉积在衬底的表面上。覆盖层沉积在IMD的该层上，然后将双镶嵌结构通过盖层图案化并进入IMD层。阻挡层被覆盖沉积，铜晶种层沉积在阻挡层上。然后用镶嵌材料填充双镶嵌结构。在盖层上除去阻挡层和铜籽晶层; 盖层可以被部分地去除或可以留在原处。在从盖表面上方去除铜种子层和阻挡层的操作期间，材料上的旋转保持在通孔和沟槽开口中的适当位置，从而保护这些开口的内表面。随后从双镶嵌结构中去除旋涂材料，并沉积铜。仍然存在于IMD表面之上的盖层保护铜在沉积期间不被铜溶液污染。使用上层CMP去除多余的铜。如果这样做是希望的话，在沉积铜之后，IMD表面上的盖层可以被去除。作为该方法的最后一步，衬垫或氧化/扩散保护层沉积在双镶嵌结构及其周围区域上。

55. 发明授权

US6040619A Semiconductor device including antireflective etch stop layer 失效
标题翻译：半导体器件包括抗反射蚀刻停止层
公开(公告)号：US6040619A
公开(公告)日：2000-03-21
申请号：US937774
申请日：1997-09-25
申请人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
发明人： Fei Wang , David K. Foote , Myron R. Cagan , Subhash Gupta
IPC分类号： H01L21/28 , H01L21/027 , H01L21/312 , H01L21/314 , H01L21/318 , H01L21/336 , H01L21/768 , H01L21/8244 , H01L23/522 , H01L27/11 , H01L29/78 , H01L23/58 , H01L21/316 , H01L23/48
CPC分类号： H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L2924/0002
摘要： A microelectronic device such as a Metal-Oxide-Semiconductor (MOS) transistor is formed on a semiconductor substrate. A tungsten damascene interconnect for the device is formed using an etch stop layer of silicon nitride, silicon oxynitride or silicon oxime having a high silicon content of approximately 40% to 50% by weight. The etch stop layer has high etch selectivity relative to overlying insulator materials such as silicon dioxide, tetraethylorthosilicate (TEOS) glass and borophosphosilicate glass (BPSG). The etch stop layer also has a high index of refraction and is anti-reflective, thereby improving critical dimension control during photolithographic imaging.
摘要翻译：在半导体衬底上形成诸如金属氧化物半导体（MOS）晶体管的微电子器件。用于器件的钨镶嵌互连使用具有大约40％至50％重量比的高硅含量的氮化硅，氮氧化硅或硅肟的蚀刻停止层形成。蚀刻停止层相对于上覆绝缘体材料如二氧化硅，原硅酸四乙酯（TEOS）玻璃和硼磷硅酸盐玻璃（BPSG）具有高蚀刻选择性。蚀刻停止层还具有高折射率并且是抗反射性的，从而改善光刻成像期间的临界尺寸控制。

56. 发明授权

US5658440A Surface image transfer etching 失效
标题翻译：表面图像转印蚀刻
公开(公告)号：US5658440A
公开(公告)日：1997-08-19
申请号：US553966
申请日：1995-11-06
申请人： Michael K. Templeton , Subhash Gupta
发明人： Michael K. Templeton , Subhash Gupta
IPC分类号： G03F7/40 , H01J37/32 , H01L21/3213 , C23C14/34
CPC分类号： H01J37/32192 , G03F7/40 , H01J37/32678 , H01L21/32137
摘要： A process called surface image transfer etching (SITE) is used to etch patterned photoresist so as to more completely transfer a well-defined pattern formed in the top surface (10a) of a material to the bulk of the material (12). The process uses no mask, but employs only a sputter etching process where the etching rates of surfaces not normal to the ion trajectories are greatly enhanced over the etching rates of surfaces normal to the ion trajectories.
摘要翻译：使用称为表面图像转移蚀刻（SITE）的工艺来蚀刻图案化的光致抗蚀剂，以便将形成在材料的顶表面（10a）中的良好限定的图案更完全地转移到材料（12）的主体上。该方法不使用掩模，而仅使用溅射蚀刻工艺，其中不垂直于离子轨迹的表面的蚀刻速率比垂直于离子轨迹的表面的蚀刻速率大大增强。

57. 发明授权

US5614765A Self aligned via dual damascene 失效
标题翻译：通过双镶嵌自对准
公开(公告)号：US5614765A
公开(公告)日：1997-03-25
申请号：US478319
申请日：1995-06-07
申请人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
发明人： Steven Avanzino , Subhash Gupta , Rich Klein , Scott D. Luning , Ming-Ren Lin
IPC分类号： H01L21/60 , H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76831 , H01L21/76807 , H01L21/76877 , H01L21/76897 , H01L23/5226 , H01L2221/1036 , H01L2924/0002
摘要： An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings. The conformal material is either a conductive material which is left in place after the via openings are formed or an insulating material which is removed. In the former, the partially filled conductive line openings are filled with additional conductive material along with the via, which is either the same or different conductive material. In the latter, the conductive line openings and vias are filled with the same conductive material.
摘要翻译：用于集成电路和用于半导体器件的衬底载体的绝缘分隔的导线和连接通孔的互连级别，使用双镶嵌仅具有一个掩模图案以形成导电线和通孔。导电线的掩模图案包含在绝缘材料中要形成通孔开口的横向扩大区域。在产生具有横向扩大区域的导电线路开口之后，开口用适形材料填充，其保护材料的蚀刻选择性基本上小于绝缘材料对用于蚀刻绝缘材料的附魔的蚀刻选择性，并且其蚀刻选择性基本上大于绝缘材料到其附魔。保形材料被各向异性地蚀刻以在扩大区域中形成侧壁并且移除侧壁之间的材料，而留下留在导电线开口部分中的材料。侧壁用作通过开口蚀刻的自对准掩模。保形材料是导电材料，其在形成通孔开口之后留在适当位置或者被去除的绝缘材料。在前者中，部分填充的导电线路开口与另外的导电材料一起填充，该通孔是相同或不同的导电材料。在后者中，导电线路开口和通孔用相同的导电材料填充。

58. 发明授权

US5468340A Highly selective high aspect ratio oxide etch method and products made by the process 失效
标题翻译：高选择性高纵横比氧化物蚀刻方法和由该方法制成的产品
公开(公告)号：US5468340A
公开(公告)日：1995-11-21
申请号：US159634
申请日：1993-11-30
申请人： Subhash Gupta , Susan Chen , Angela Hui
发明人： Subhash Gupta , Susan Chen , Angela Hui
IPC分类号： C23F4/00 , H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/768 , H01L23/522 , H01L21/00 , H05H1/00
CPC分类号： H01L21/76805 , H01L21/31116 , H01L21/76816
摘要： A method for rapid anisotropic dry etching of oxide compounds in high aspect ratio openings which etching method is highly selective to metal salicides and which method employs plasma gases of CHF.sub.3, N.sub.2 and a high flow rate of He at a high pressure and products made by the process.
摘要翻译：一种用于在高纵横比开口中快速各向异性干蚀刻氧化物化合物的方法，其蚀刻方法对金属杀锌剂具有高选择性，并且哪种方法使用CHF 3，N 2等离子体气体和高流量的He，以及由处理。

59. 发明授权

US5308740A Electrical measurement of sidewall angle 失效
标题翻译：侧壁角度的电气测量
公开(公告)号：US5308740A
公开(公告)日：1994-05-03
申请号：US947242
申请日：1992-09-18
申请人： Michael K. Templeton , Subhash Gupta
发明人： Michael K. Templeton , Subhash Gupta
IPC分类号： G03F7/26 , G03C5/00 , B44C1/22
CPC分类号： G03F7/26
摘要： A method for measuring the sidewall angle of patterned photoresist (16), as well as wall angles of other materials, is provided. The method comprises forming two copies of the patterned photoresist feature for which the sidewall measurement is to be obtained on a conducting substrate (14). The first copy is processed via conventional techniques for linewidth measurement, which consists of a pattern transfer etch of the first copy into the underlying conductive substrate, followed by electrical measurement of the conductor linewidth to yield linewidth 1 (LW1). The second copy is processed such that there is a shape altering etch prior to the pattern transfer etch. A linewidth 2 (LW2) is obtained. The angle is then extracted from the two linewidth measurements.
摘要翻译：提供了用于测量图案化光致抗蚀剂（16）的侧壁角以及其它材料的壁角的方法。该方法包括在导电衬底（14）上形成要获得侧壁测量的图案化光致抗蚀剂特征的两个拷贝。通过用于线宽测量的常规技术来处理第一个拷贝，该技术包括将第一拷贝的图案转移蚀刻到下面的导电衬底中，随后电导体线宽的线性测量以产生线宽1（LW1）。处理第二拷贝使得在图案转移蚀刻之前存在改变蚀刻的形状。得到线宽2（LW2）。然后从两个线宽测量中提取角度。

60. 发明授权

US5260868A Method for calendaring future events in real-time 失效
标题翻译：实时记录未来事件的方法
公开(公告)号：US5260868A
公开(公告)日：1993-11-09
申请号：US776713
申请日：1991-10-15
申请人： Subhash Gupta , Sanjiv S. Sidhu , Frank Vlach
发明人： Subhash Gupta , Sanjiv S. Sidhu , Frank Vlach
IPC分类号： G05B19/418 , G06Q10/06 , G07C3/00 , G06F15/20
CPC分类号： G06Q10/06 , G05B19/41865 , G07C3/00 , G05B2219/34418 , Y02P90/20
摘要： A mechanism and method for calendaring a plurality of events such as scheduling the operation of interrelated machines which perform a process flow. Future time is divided into segments, called buckets, of increasing length. The first two buckets are of the same size and each of the following buckets twice as large as its preceding bucket. The first bucket slides so as to always cover a specified length of time following the current time. Events scheduled in the calendar is added to the appropriate bucket, depending on how far in the future it is to take place. When the current time equals the scheduled time for an event, then that event is removed from the bucket where it resides. When a bucket has become empty because all events have been removed from it, the events in the following bucket are distributed over the two buckets preceding it.
摘要翻译：一种用于对多个事件进行日历的机制和方法，例如调度执行处理流程的相互关联的机器的操作。未来时间被分为长度增长的段，称为桶。前两个桶的尺寸相同，以下桶中的每一个都是前一桶的两倍。第一个铲斗滑动，以便在当前时间之后始终覆盖指定的时间长度。日程安排的活动将添加到相应的存储桶中，具体取决于将来发生的时间。当当前时间等于事件的预定时间时，该事件将从它驻留的存储桶中删除。当桶已经变为空时，因为所有事件都已从其中删除，下一个桶中的事件将分布在其前面的两个桶中。

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