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51. 发明授权

US08054665B2 Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers 有权
标题翻译：堆叠存储器件包括夹在多个解码器/驱动器之间的预解码器/预驱动器
公开(公告)号：US08054665B2
公开(公告)日：2011-11-08
申请号：US12654645
申请日：2009-12-28
申请人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
发明人： Seung-eon Ahn , Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Hyun-ho Choi
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C13/0023 , G11C2213/71 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L25/18 , H01L2224/48091 , H01L2224/49 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-decoders electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-decoder electrically connected to the plurality of inter-decoders and disposed between the plurality of inter-decoders. A stacked memory device may include a substrate, a plurality of memory layers stacked on and above the substrate and divided into a plurality of groups, a plurality of inter-drivers electrically connected to and disposed between the plurality of memory layers in a corresponding one of the plurality of groups, and at least one pre-driver electrically connected to the plurality of inter-drivers, and disposed between the plurality of inter-drivers.
摘要翻译：层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个解码器电连接到多个存储器层并且布置在多个存储器层中的相应的一个所述多个组以及至少一个预解码器电连接到所述多个解码器并且设置在所述多个解码器之间。层叠的存储器件可以包括衬底，堆叠在衬底上和衬底上并被分成多个组的多个存储器层，多个驱动器电连接到多个存储器层并且被布置在多个存储器层中的相应的一个所述多个组，以及电连接到所述多个驱动器之间的至少一个预驱动器，并且设置在所述多个驱动器之间。

52. 发明授权

US08050079B2 Nonvolatile memory device using variable resistive element 失效
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08050079B2
公开(公告)日：2011-11-01
申请号：US12577888
申请日：2009-10-13
申请人： Young-Sun Song , Ho-Jung Kim , Sang-Beom Kang
发明人： Young-Sun Song , Ho-Jung Kim , Sang-Beom Kang
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C7/18 , G11C5/147 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2207/002
摘要： A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit.
摘要翻译：使用电阻材料的非易失性存储器件包括具有排列成矩阵的非易失性存储单元，多位线，列选择电路和列驱动器的存储单元阵列。位线耦合到存储单元阵列中的非易失性存储单元的列。列选择电路响应于列选择信号选择至少一个位线。每列驱动器提供列选择信号，并且包括第一充电单元，其响应于第一充电信号而将列驱动器的输出端口充电到第一电压电平;第二充电单元，对列驱动器的输出端口进行充电响应于第二充电信号而从第一电压电平到第二电压电平;以及电流控制器，其控制从第二充电单元到第一充电单元的电流路径。

53. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

54. 发明申请

US20110170332A1 Methods of Driving Nonvolatile Memory Devices that Utilize Read/Write Merge Circuits 审中-公开
标题翻译：驱动使用读/写合并电路的非易失性存储器件的方法
公开(公告)号：US20110170332A1
公开(公告)日：2011-07-14
申请号：US13011188
申请日：2011-01-21
申请人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho , Joon-min Park
发明人： Hyung-rok Oh , Sang-beom Kang , Woo-yeong Cho , Joon-min Park
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/12 , G11C5/145 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79
摘要： An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.
摘要翻译：集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列（例如，可变电阻单元）。提供读/写控制电路。读/写控制电路包括读/写合并电路和列选择电路。被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

55. 发明授权

US07894236B2 Nonvolatile memory devices that utilize read/write merge circuits 失效
标题翻译：使用读/写合并电路的非易失性存储器件
公开(公告)号：US07894236B2
公开(公告)日：2011-02-22
申请号：US11945443
申请日：2007-11-27
申请人： Hyung-rok Oh , Woo-yeong Cho , Sang-beom Kang , Joon-min Park
发明人： Hyung-rok Oh , Woo-yeong Cho , Sang-beom Kang , Joon-min Park
IPC分类号： G11C7/00 , G11C7/12
CPC分类号： G11C7/12 , G11C5/145 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/003 , G11C2213/31 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79
摘要： An integrated circuit memory device includes an array of nonvolatile memory cells (e.g., variable resistance cells) having a first plurality of lines electrically coupled to memory cells therein. A read/write control circuit is provided. The read/write control circuit includes a read/write merge circuit and a column selection circuit. The read/write control circuit, which is configured to drive a selected one of the first plurality of lines with unequal write and read voltages during respective write and read operations, includes a compensating unit. This compensating unit is configured to provide a read compensation current to the selected one of the first plurality of lines circuit during the read operation.
摘要翻译：集成电路存储器件包括具有电耦合到其中的存储器单元的第一多个线的非易失性存储器单元阵列（例如，可变电阻单元）。提供读/写控制电路。读/写控制电路包括读/写合并电路和列选择电路。被配置为在相应的写入和读取操作期间以不相等的写入和读取电压驱动所述第一多个线路中的所选择的一个线路的所述读取/写入控制电路包括补偿单元。该补偿单元被配置为在读取操作期间向第一多个线路电路中的所选择的一个电路提供读取补偿电流。

56. 发明申请

US20100284216A1 INFORMATION STORAGE DEVICES USING MAGNETIC DOMAIN WALL MOVEMENT AND METHODS OF OPERATING THE SAME 有权
标题翻译：使用磁畴壁移动的信息存储设备及其操作方法
公开(公告)号：US20100284216A1
公开(公告)日：2010-11-11
申请号：US12775160
申请日：2010-05-06
申请人： Ho Jung Kim , Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Jong Wan Kim , Young Pill Kim , Sung Chul Lee
发明人： Ho Jung Kim , Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Jong Wan Kim , Young Pill Kim , Sung Chul Lee
IPC分类号： G11C11/14 , G11C7/00 , G11C8/00
CPC分类号： G11C11/1653 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： An information storage device includes a first portion comprising at first at least one magnetic track, each of the at least one magnetic track in the first portion including a first plurality of magnetic domains and being configured to store a first type of data therein and a second portion comprising a second at least one magnetic track, each of the at least one magnetic track in the second portion including a second plurality of magnetic domains and being configured to store a second type of data therein, the second type of data being related to the first type of data.
摘要翻译：信息存储装置包括第一部分，其首先包括至少一个磁道，第一部分中的至少一个磁道中的每一个包括第一多个磁畴，并且被配置为在其中存储第一类型的数据，部分包括第二至少一个磁道，第二部分中的至少一个磁道中的每一个包括第二多个磁畴，并且被配置为在其中存储第二类型的数据，第二类型的数据与第一类数据。

57. 发明申请

US20100226165A1 RESISTIVE MEMORY DEVICES HAVING A STACKED STRUCTURE AND METHODS OF OPERATION THEREOF 有权
标题翻译：具有堆叠结构的电阻式存储器件及其操作方法
公开(公告)号：US20100226165A1
公开(公告)日：2010-09-09
申请号：US12714950
申请日：2010-03-01
申请人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
发明人： Sang Beom Kang , Chul Woo Park , Hyun Ho Choi , Ho Jung Kim
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C7/1045 , G11C5/02 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2211/5641 , G11C2213/71 , G11C2213/72 , G11C2213/79
摘要： A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.
摘要翻译：存储器件包括堆叠在半导体衬底上的多个电阻存储器单元层的堆叠电阻性存储单元阵列，其中相应的存储单元层被配置为根据包括每个单元的位数的各自的程序模式来存储数据。该存储装置还包括控制电路，该控制电路被配置为响应于地址信号来识别所选择的存储器单元层的编程模式，并且根据所识别的程序模式响应于地址信号访问所选择的存储单元层。程序模式可以包括单级单元模式和至少一个多级单元模式。

58. 发明申请

US20100208381A1 Magnetic packet memory storage devices, memory systems including such devices, and methods of controlling such devices 失效
标题翻译：磁性分组存储器存储设备，包括这种设备的存储器系统以及控制这些设备的方法
公开(公告)号：US20100208381A1
公开(公告)日：2010-08-19
申请号：US12658807
申请日：2010-02-16
申请人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
发明人： Ho-jung Kim , Chul-woo Park , Sang-beom Kang , Jong-wan Kim , Hyun-ho Choi , Young-pil Kim , Sung-chul Lee
IPC分类号： G11B19/02
CPC分类号： G11C11/15 , G11C5/04
摘要： A memory device is comprised of a magnetic structure that stores information in a plurality of domains of the magnetic structure. A write unit writes information to at least one of the plurality of domains of the magnetic structure by applying a write current to the magnetic structure in response to a control signal. A read unit reads information from at least one of the plurality of domains of the magnetic structure by applying a read current to the magnetic structure in response to the control signal. A domain wall movement control unit is coupled to a portion of the magnetic structure and moves information stored in the plurality of domains in the magnetic structure to other domains in the magnetic structure in response to the control signal. The write unit, the read unit and the domain wall movement control unit are all coupled to the same control signal line that provides the control signal.
摘要翻译：存储器件由将磁信息存储在磁结构的多个域中的磁结构构成。写单元响应于控制信号向磁结构施加写入电流，将信息写入磁结构的多个域中的至少一个。读取单元通过响应于控制信号向磁性结构施加读取电流，从磁性结构的多个域中的至少一个域读取信息。畴壁移动控制单元耦合到磁结构的一部分，并且响应于控制信号将存储在磁结构中的多个域中的信息移动到磁结构中的其他区域。写单元，读单元和域壁移动控制单元都耦合到提供控制信号的相同控制信号线。

59. 发明授权

US07710767B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07710767B2
公开(公告)日：2010-05-04
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

60. 发明授权

US07701747B2 Non-volatile memory including sub cell array and method of writing data thereto 有权
标题翻译：包括子单元阵列的非易失性存储器和向其写入数据的方法
公开(公告)号：US07701747B2
公开(公告)日：2010-04-20
申请号：US11958432
申请日：2007-12-18
申请人： Joon-min Park , Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh
发明人： Joon-min Park , Sang-beom Kang , Woo-yeong Cho , Hyung-rok Oh
IPC分类号： G11C7/00
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0088 , G11C2013/009
摘要： A non-volatile memory device, in which data values are determined by polarities at cell terminals, includes a memory cell array. The memory cell array is divided into multiple sub cell arrays, each sub cell array including at least one input/output line and an X-decoder/driver. First input/output lines included in different sub cell arrays may be simultaneously activated and bias voltages may be applied to the activated first input/output lines in accordance with the data values. The non-volatile memory device may be a bi-directional resistive random access memory (RRAM).
摘要翻译：其中数据值由单元终端的极性确定的非易失性存储器件包括存储单元阵列。存储单元阵列被分成多个子单元阵列，每个子单元阵列包括至少一个输入/输出线和X解码器/驱动器。可以同时激活包括在不同子单元阵列中的第一输入/输出线，并且可以根据数据值将偏置电压施加到激活的第一输入/输出线。非易失性存储器件可以是双向电阻随机存取存储器（RRAM）。

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