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1. 发明授权

US08050079B2 Nonvolatile memory device using variable resistive element 失效
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08050079B2
公开(公告)日：2011-11-01
申请号：US12577888
申请日：2009-10-13
申请人： Young-Sun Song , Ho-Jung Kim , Sang-Beom Kang
发明人： Young-Sun Song , Ho-Jung Kim , Sang-Beom Kang
IPC分类号： G11C11/00 , G11C11/36
CPC分类号： G11C7/18 , G11C5/147 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2207/002
摘要： A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit.
摘要翻译：使用电阻材料的非易失性存储器件包括具有排列成矩阵的非易失性存储单元，多位线，列选择电路和列驱动器的存储单元阵列。位线耦合到存储单元阵列中的非易失性存储单元的列。列选择电路响应于列选择信号选择至少一个位线。每列驱动器提供列选择信号，并且包括第一充电单元，其响应于第一充电信号而将列驱动器的输出端口充电到第一电压电平;第二充电单元，对列驱动器的输出端口进行充电响应于第二充电信号而从第一电压电平到第二电压电平;以及电流控制器，其控制从第二充电单元到第一充电单元的电流路径。

2. 发明申请

US20100091552A1 NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT 失效
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20100091552A1
公开(公告)日：2010-04-15
申请号：US12577888
申请日：2009-10-13
申请人： Young-Sun Song , Ho-Jung Kim , Sang-Beom Kang
发明人： Young-Sun Song , Ho-Jung Kim , Sang-Beom Kang
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C7/18 , G11C5/147 , G11C8/10 , G11C13/0004 , G11C13/0026 , G11C2207/002
摘要： A nonvolatile memory device, using a resistance material, includes a memory cell array having nonvolatile memory cells arranged in a matrix, multiple bit lines, a column selection circuit and column drivers. The bit lines are coupled to columns of the nonvolatile memory cells in the memory cell array. The column selection circuit selects at least one bit line in response to column selection signals. Each column driver supplies a column selection signal, and includes a first charge unit that charges an output port of the column driver to a first voltage level in response to a first charge signal, a second charge unit that charges the output port of the column driver to a second voltage level from the first voltage level in response to a second charge signal, and a current controller that controls a current path from the second charge unit to the first charge unit.
摘要翻译：使用电阻材料的非易失性存储器件包括具有排列成矩阵的非易失性存储单元，多位线，列选择电路和列驱动器的存储单元阵列。位线耦合到存储单元阵列中的非易失性存储单元的列。列选择电路响应于列选择信号选择至少一个位线。每列驱动器提供列选择信号，并且包括第一充电单元，其响应于第一充电信号而将列驱动器的输出端口充电到第一电压电平;第二充电单元，对列驱动器的输出端口进行充电响应于第二充电信号而从第一电压电平到第二电压电平;以及电流控制器，其控制从第二充电单元到第一充电单元的电流路径。

3. 发明申请

US20100220513A1 Bi-Directional Resistive Memory Devices and Related Memory Systems and Methods of Writing Data 有权
标题翻译：双向电阻式存储器件及相关存储器系统及数据写入方法
公开(公告)号：US20100220513A1
公开(公告)日：2010-09-02
申请号：US12715742
申请日：2010-03-02
申请人： Ho-Jung Kim , Chul-Woo Park , Sang-Beom Kang , Hyun-Ho Choi
发明人： Ho-Jung Kim , Chul-Woo Park , Sang-Beom Kang , Hyun-Ho Choi
IPC分类号： G11C11/00 , G11C7/10 , G11C5/14
CPC分类号： G11C7/1078 , G11C5/145 , G11C7/1084 , G11C8/06 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C15/04 , G11C2013/0073 , G11C2013/0083
摘要： A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided.
摘要翻译：双向电阻式存储器件包括包括多个存储单元和输入/输出（I / O）电路的存储单元阵列。 I / O电路被配置为产生具有正极性的第一电压和具有负极性的第二电压，响应于输入的逻辑状态，通过位线将第一电压和第二电压中的一个提供给存储单元阵列数据，并且当写入存储单元阵列中的数据具有偏移量时，调整第一和第二电压的幅度。还提供了相关的存储器系统和方法。

4. 发明授权

US08223529B2 Resistive memory devices, memory systems and methods of controlling input and output operations of the same 有权
标题翻译：电阻式存储器件，存储器系统和控制其输入和输出操作的方法
公开(公告)号：US08223529B2
公开(公告)日：2012-07-17
申请号：US12703354
申请日：2010-02-10
申请人： Ho-Jung Kim , Yeong-Taek Lee , Chul-Woo Park , Sang-Beom Kang
发明人： Ho-Jung Kim , Yeong-Taek Lee , Chul-Woo Park , Sang-Beom Kang
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C8/10 , G11C13/00 , G11C13/0004 , G11C13/0069 , G11C2013/005 , G11C2013/0054 , G11C2013/0076 , G11C2013/009
摘要： A resistive memory device includes a resistive memory cell array, an output circuit and an input circuit. The resistive memory cell array includes a plurality of memory cells that are coupled to bitlines. The output circuit generates a sensing output signal during a write operation by sensing a bitline voltage, and generates output data during a read operation by sensing the bitline voltage. The input circuit controls the bitline voltage based on input data for the write operation, and limits the bitline voltage in response to the sensing output signal during the write operation. The memory cells are protected by effectually limiting bitline voltage.
摘要翻译：电阻式存储器件包括电阻存储单元阵列，输出电路和输入电路。电阻存储单元阵列包括耦合到位线的多个存储单元。输出电路通过感测位线电压在写入操作期间产生感测输出信号，并通过感测位线电压在读取操作期间产生输出数据。输入电路基于用于写入操作的输入数据来控制位线电压，并且在写入操作期间响应于感测输出信号来限制位线电压。存储单元受到有效限制位线电压的保护。

5. 发明申请

US20100246246A1 Memory device, memory system having the same, and programming method of a memory cell 失效
标题翻译：存储器件，具有相同的存储器系统以及存储器单元的编程方法
公开(公告)号：US20100246246A1
公开(公告)日：2010-09-30
申请号：US12659473
申请日：2010-03-10
申请人： Ho-Jung Kim , Sang-Beom Kang , Chul Woo Park , Hyun Ho Choi
发明人： Ho-Jung Kim , Sang-Beom Kang , Chul Woo Park , Hyun Ho Choi
IPC分类号： G11C11/00 , G06F12/00 , G06F12/06 , G11C7/00
CPC分类号： G11C11/5678 , G06F12/0238 , G06F2212/7202 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2211/5641 , G11C2211/5642 , G11C2211/5648 , G11C2213/32 , G11C2213/56 , G11C2213/72 , G11C2213/79
摘要： A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell.
摘要翻译：具有多个多级存储器单元的非易失性存储器件，多个至少两个存储器单元可以通过为多个存储器单元中的每个多电平存储器单元写入最低有效位并且在最低有效位之后被编程已写入多个存储器单元中的每个多级存储器单元，为每个多级存储器单元写下一个有效位。

6. 发明申请

US20100214831A1 Memory device, memory system having the same, and programming method of a memory cell 审中-公开
标题翻译：存储器件，具有相同的存储器系统以及存储器单元的编程方法
公开(公告)号：US20100214831A1
公开(公告)日：2010-08-26
申请号：US12588536
申请日：2009-10-19
申请人： Ho-Jung Kim , Chul-Woo Park , Sang-Beom Kang , Hyun-Ho Choi
发明人： Ho-Jung Kim , Chul-Woo Park , Sang-Beom Kang , Hyun-Ho Choi
IPC分类号： G11C11/00 , G11C8/00 , G11C7/10 , G11C7/00
CPC分类号： G11C13/0064 , G11C11/56 , G11C11/5678 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0061 , G11C13/0069 , G11C2013/0076 , G11C2013/0088 , G11C2013/0092 , G11C2211/5622 , G11C2211/5642 , G11C2213/72 , G11C2213/79
摘要： A memory device includes an array of resistance change memory cells divided into a first memory block including a first selected memory cell of a first plurality of memory cells and a second memory block including a second selected memory cell of a second plurality of memory cells, and sensing and writing circuitry configured to simultaneously activate a line connected with the first and second selected memory cells. The first and second selected memory cells may be written by iteratively applying a level-controlled write signal to memory cells not having a programmed state equal to the write data until a verify-read operation indicates respective programmed states for the first and second selected memory cells are equal to the write data.
摘要翻译：存储器件包括被分成包括第一多个存储器单元的第一选定存储单元的第一存储器单元和包括第二多个存储器单元的第二选定存储单元的第二存储器块的电阻变化存储器单元阵列，以及感测和写入电路，其被配置为同时激活与第一和第二选定存储单元相连的线。第一和第二选择的存储器单元可以通过迭代地将电平控制的写入信号施加到不具有等于写入数据的编程状态的存储器单元来写入，直到验证读取操作指示第一和第二选择的存储单元的相应的编程状态等于写入数据。

7. 发明授权

US08271856B2 Resistive memory devices and methods of controlling operations of the same 有权
标题翻译：电阻式存储器件及其操作方法
公开(公告)号：US08271856B2
公开(公告)日：2012-09-18
申请号：US12711416
申请日：2010-02-24
申请人： Sang-Beom Kang , Chul-Woo Park , Hyun-Ho Choi , Ho-Jung Kim
发明人： Sang-Beom Kang , Chul-Woo Park , Hyun-Ho Choi , Ho-Jung Kim
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , G11C13/0004 , G11C2029/0411
摘要： To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.
摘要翻译：为了控制电阻性存储器件的操作，错误检查和校正（ECC）代码的输入输出操作与数据的输入输出操作分离。确定ECC代码的输入输出操作的条件比数据的输入输出操作的条件更严格。可以提高ECC代码的输入输出操作的可靠性，从而减少由于缺陷存储单元，噪声等导致的错误。

8. 发明授权

US08228711B2 Bi-directional resistive memory devices and related memory systems and methods of writing data 有权
标题翻译：双向电阻式存储器件和相关的存储器系统以及写入数据的方法
公开(公告)号：US08228711B2
公开(公告)日：2012-07-24
申请号：US12715742
申请日：2010-03-02
申请人： Ho-Jung Kim , Chul-Woo Park , Sang-Beom Kang , Hyun-Ho Choi
发明人： Ho-Jung Kim , Chul-Woo Park , Sang-Beom Kang , Hyun-Ho Choi
IPC分类号： G11C11/00
CPC分类号： G11C7/1078 , G11C5/145 , G11C7/1084 , G11C8/06 , G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/0038 , G11C13/0064 , G11C13/0069 , G11C15/04 , G11C2013/0073 , G11C2013/0083
摘要： A bi-directional resistive memory device includes a memory cell array including a plurality of memory cells and an input/output (I/O) circuit. The I/O circuit is configured to generate a first voltage having a positive polarity and a second voltage having a negative polarity, provide one of the first voltage and the second voltage to the memory cell array through a bitline responsive to a logic state of input data, and adjust magnitudes of the first and second voltage when data written in the memory cell array has an offset. Related memory systems and methods are also provided.
摘要翻译：双向电阻式存储器件包括包括多个存储单元和输入/输出（I / O）电路的存储单元阵列。 I / O电路被配置为产生具有正极性的第一电压和具有负极性的第二电压，响应于输入的逻辑状态，通过位线将第一电压和第二电压中的一个提供给存储单元阵列数据，并且当写入存储单元阵列中的数据具有偏移量时，调整第一和第二电压的幅度。还提供了相关的存储器系统和方法。

9. 发明授权

US08111563B2 Multi-level nonvolatile memory device with fast execution of program speed and programming method of the same 失效
标题翻译：多级非易失性存储器件具有快速执行程序速度和编程方式相同的功能
公开(公告)号：US08111563B2
公开(公告)日：2012-02-07
申请号：US12659473
申请日：2010-03-10
申请人： Ho-Jung Kim , Sang-Beom Kang , Chul Woo Park , Hyun Ho Choi
发明人： Ho-Jung Kim , Sang-Beom Kang , Chul Woo Park , Hyun Ho Choi
IPC分类号： G11C7/00
CPC分类号： G11C11/5678 , G06F12/0238 , G06F2212/7202 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/009 , G11C2211/5641 , G11C2211/5642 , G11C2211/5648 , G11C2213/32 , G11C2213/56 , G11C2213/72 , G11C2213/79
摘要： A nonvolatile memory device having a plurality of multi-level memory cells, the plurality being at least two, may be programmed by writing a least significant bit for each multi-level memory cell of the plurality of memory cells and, after the least significant bit has been written for each multi-level memory cell of the plurality of memory cells, writing a next significant bit for each multi-level memory cell.
摘要翻译：具有多个多级存储器单元的非易失性存储器件，多个至少两个存储器单元可以通过为多个存储器单元中的每个多电平存储器单元写入最低有效位并且在最低有效位之后被编程已写入多个存储器单元中的每个多级存储器单元，为每个多级存储器单元写下一个有效位。

10. 发明申请

US20100218073A1 Resistive Memory Devices and Methods of Controlling Operations of the Same 有权
标题翻译：电阻式存储器件及其控制方法
公开(公告)号：US20100218073A1
公开(公告)日：2010-08-26
申请号：US12711416
申请日：2010-02-24
申请人： Sang-Beom Kang , Chul-Woo Park , Hyun-Ho Choi , Ho-Jung Kim
发明人： Sang-Beom Kang , Chul-Woo Park , Hyun-Ho Choi , Ho-Jung Kim
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1048 , G11C13/0004 , G11C2029/0411
摘要： To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc.
摘要翻译：为了控制电阻性存储器件的操作，错误检查和校正（ECC）代码的输入输出操作与数据的输入输出操作分离。确定ECC代码的输入输出操作的条件比数据的输入输出操作的条件更严格。可以提高ECC代码的输入输出操作的可靠性，从而减少由于缺陷存储单元，噪声等导致的错误。

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