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41. 发明申请

US20040121615A1 Method of forming fine patterns 审中-公开
标题翻译：形成精细图案的方法
公开(公告)号：US20040121615A1
公开(公告)日：2004-06-24
申请号：US10681145
申请日：2003-10-09
发明人： Fumitake Kaneko , Yoshiki Sugeta , Toshikazu Tachikawa
IPC分类号： H01L021/31
CPC分类号： G03F7/40 , H01L21/0274
摘要： It is disclosed a method of forming fine patterns comprising: covering a substrate having photoresist patterns with an over-coating agent for forming fine patterns, applying heat treatment to cause thermal shrinkage of the over-coating agent so that the spacing between adjacent photoresist patterns is lessened by the resulting thermal shrinking action, and removing the over-coating agent substantially completely by way of bringing thusly treated substrate into contact with a remover solution for over 60 seconds.
摘要翻译：公开了一种形成精细图案的方法，包括：用用于形成精细图案的过涂层覆盖具有光致抗蚀剂图案的基板，进行热处理以引起外涂层的热收缩，使得相邻光致抗蚀剂图案之间的间隔为通过所得到的热收缩作用减轻，并且通过将经处理的基底与去除剂溶液接触超过60秒，基本上完全除去覆盖剂。

42. 发明申请

US20040121543A1 Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20040121543A1
公开(公告)日：2004-06-24
申请号：US10733233
申请日：2003-12-12
申请人： RENESAS TECHNOLOGY CORP.
发明人： Yoshihiro Miyagawa
IPC分类号： H01L021/31
CPC分类号： H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/0228 , H01L21/31612 , H01L21/31625 , H01L21/76832 , H01L21/76837
摘要： First, an first insulating film is formed along surfaces of a plurality of combinations of an gate electrode and an gate insulating films, and a semiconductor substrate, respectively. Then, on the first insulating film, an second insulating film different from the first insulating film is formed. The steps of forming the first insulating film and forming the second insulating film are alternately repeated until a concave formed by the surface of an later insulating film, which is a film formed later out of the first insulating film and the second insulating film, is positioned above the upper surface of the gate electrode. Thereafter, an third insulating film is formed on the later insulating film. Thus, a semiconductor device with high reliability can be obtained by improving a state of the insulating film formed between the gate electrodes.
摘要翻译：首先，分别在栅极电极和栅极绝缘膜以及半导体衬底的多个组合的表面上形成第一绝缘膜。然后，在第一绝缘膜上形成与第一绝缘膜不同的第二绝缘膜。交替地重复形成第一绝缘膜并形成第二绝缘膜的步骤，直到由稍后从第一绝缘膜和第二绝缘膜形成的膜的较晚绝缘膜的表面形成的凹部被定位在栅电极的上表面之上。此后，在后面的绝缘膜上形成第三绝缘膜。因此，通过改善形成在栅电极之间的绝缘膜的状态，可以获得高可靠性的半导体器件。

43. 发明申请

US20040119145A1 Method for depositing a very high phosphorus doped silicon oxide film 失效
标题翻译：沉积非常高的磷掺杂氧化硅膜的方法
公开(公告)号：US20040119145A1
公开(公告)日：2004-06-24
申请号：US09950755
申请日：2001-09-13
申请人： TECH SEMICONDUCOR SINGAPORE PTE. LTD.
发明人： Jian Sun , Hing Ho Au , Yew Hoong Phang
IPC分类号： B32B017/06 , H01L023/58 , H01L021/31
CPC分类号： C23C16/45561 , C23C16/401 , C23C16/455 , C23C16/45557 , H01L21/02129 , H01L21/02271 , H01L21/02362 , H01L21/31625
摘要： A thermal activated SACVD method for depositing a phosphorus oxide layer onto a silicon oxide wafer comprising the steps of: loading an SACVD device with a silicon oxide wafer; depositing a phosphorus doped oxide (PSG) layer on the USG layer using pure oxygen and a phosphorus and silicon source; purging the SACVD device; and depositing a boron and phosphorus doped oxide (BPSG) layer on the PSG layer.
摘要翻译：一种用于在氧化硅晶片上沉积磷氧化物层的热激活SACVD方法，包括以下步骤：用硅氧化物晶片装载SACVD器件; 使用纯氧和磷源和硅源在USG层上沉积磷掺杂氧化物（PSG）层; 清洗SACVD设备; 以及在PSG层上沉积硼和磷掺杂氧化物（BPSG）层。

44. 发明申请

US20040115956A1 Substrate treating device and substrate treating method 审中-公开
标题翻译：基板处理装置及基板处理方法
公开(公告)号：US20040115956A1
公开(公告)日：2004-06-17
申请号：US10473161
申请日：2003-09-29
发明人： Hiroshi Ishida
IPC分类号： H01L021/31 , H01L021/469
CPC分类号： H01L21/67173 , H01L21/67178 , H01L21/67184 , H01L21/67213 , H01L21/76807 , H01L21/76825 , H01L21/76829 , H01L21/76832 , H01L21/76835
摘要： Since a first processing unit group that forms an interlayer insulating film under atmospheric pressure and a second processing unit group that performs, for example, electron beam or UV irradiation, CVD, cleaning and the like under reduced pressure or under increased pressure are configured to be integrally disposed, a time period necessary for processing can be shortened, particularly in the damascene process, and footprint per processing capacity can be reduced. Furthermore, as the processing time period is shortened in such manner, even when, for example, a porous film is used as an insulating film, the film can be restrained from absorbing moisture in the air thus deterioration in the film quality can be prevented, resulting in forming an insulating film of high quality.
摘要翻译：由于在大气压下形成层间绝缘膜的第一处理单元组和在减压或加压下进行例如电子束或UV照射，CVD，清洗等的第二处理单元组被配置为整体地设置，可以缩短处理所需的时间段，特别是在镶嵌工艺中，可以减少每个处理能力的占地面积。此外，由于处理时间缩短为这样，即使例如使用多孔膜作为绝缘膜，也可以抑制膜吸收空气中的水分，从而可以防止膜质量的劣化，导致形成高质量的绝缘膜。

45. 发明申请

US20040115953A1 Electro-optical device and driving method for the same 失效
标题翻译：电光装置及其驱动方法相同
公开(公告)号：US20040115953A1
公开(公告)日：2004-06-17
申请号：US10728989
申请日：2003-12-08
发明人： Shunpei Yamazaki , Akira Mase , Masaaki Hiroki
IPC分类号： H01L021/31
CPC分类号： H01L27/1248 , G02F1/13624 , G02F2001/134345 , G02F2001/136245 , G09G3/3614 , G09G3/3648 , G09G3/3659 , G09G2300/0809 , G09G2300/0823 , G09G2330/08 , H01L27/1214 , H01L27/14643 , H01L27/14687 , H01L27/14689 , H01L27/3244
摘要： A display and a driving method for the same capable of constructing clear visual images is described. In the display, a plurality of conductive pads are opposed to a back electrode with a light influencing medium such as a liquid crystal layer. Control signals are supplied to the conductive pads through. complimentary transistors comprise a p-channel field effect transistor and an n-channel field effect transistor connected between VDD and VSS lines of a control circuit, which also supplies a bias voltage to the back electrode and gate control signals to the gate terminals of the p-channel field effect transistor and the n-channel field effect transistor. During operation, the bias voltage is inverted in order to invert the polarity of control signal applied across the light influencing medium.
摘要翻译：描述了能够构建清晰可视图像的显示器及其驱动方法。在显示器中，多个导电焊盘与具有诸如液晶层的光影响介质的背面电极相对。控制信号被提供给导电焊盘。互补晶体管包括连接在控制电路的VDD和VSS线之间的p沟道场效应晶体管和n沟道场效应晶体管，其也向背电极提供偏置电压，并将栅极控制信号提供给p的栅极端通道场效应晶体管和n沟道场效应晶体管。在操作期间，偏置电压被反转以反转施加在光影响介质上的控制信号的极性。

46. 发明申请

US20040110391A1 Atomic layer deposited Zr-Sn-Ti-O films 有权
标题翻译：原子层沉积Zr-Sn-Ti-O薄膜
公开(公告)号：US20040110391A1
公开(公告)日：2004-06-10
申请号：US10309935
申请日：2002-12-04
申请人： Micron Technology, Inc.
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L021/31
CPC分类号： H01L21/02194 , C04B35/49 , C04B2235/3293 , C04B2235/441 , C04B2235/444 , C23C16/40 , C23C16/45529 , C23C16/45531 , H01L21/02186 , H01L21/02189 , H01L21/02205 , H01L21/0228 , H01L21/3141 , H01L21/31604 , H01L21/31683 , H01L21/31691
摘要： A dielectric film containing atomic layer deposited ZrnullSnnullTinullO and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing titanium and oxygen onto a substrate surface by atomic layer deposition, depositing zirconium and oxygen onto a substrate surface by atomic layer deposition, and depositing tin and oxygen onto a substrate surface by atomic layer deposition form the ZrnullSnnullTinullO dielectric layer. Dielectric films containing atomic layer deposited ZrnullSnnullTinullO are thermodynamically stable such that the ZrnullSnnullTinullO will have minimal reactions with a silicon substrate or other structures during processing.
摘要翻译：含有沉积Zr-Sn-Ti-O的原子层的电介质膜和制造这种电介质膜的方法产生可靠的介电层，其具有比使用SiO 2可获得的薄的当量的氧化物厚度。通过原子层沉积将钛和氧沉积到衬底表面上，通过原子层沉积将锆和氧沉积到衬底表面上，并通过原子层沉积将锡和氧沉积到衬底表面上形成Zr-Sn-Ti-O介电层。包含原子层沉积的Zr-Sn-Ti-O的介电膜在热力学上是稳定的，使得Zr-Sn-Ti-O在加工过程中与硅衬底或其它结构的反应最小。

47. 发明申请

US20040110348A1 Atomic layer deposited Zr-Sn-Ti-O films using TiI4 失效
标题翻译：使用TiI4沉积Zr-Sn-Ti-O薄膜的原子层
公开(公告)号：US20040110348A1
公开(公告)日：2004-06-10
申请号：US10309583
申请日：2002-12-04
申请人： Micron Technology, Inc.
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L021/31 , H01L021/336 , H01L021/3205 , H01L021/469 , H01L021/4763
CPC分类号： H01L21/02194 , C23C16/40 , C23C16/45531 , C23C16/45553 , H01L21/02186 , H01L21/02189 , H01L21/02205 , H01L21/0228 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3142 , H01L21/31604 , H01L21/31641 , H01L29/513 , H01L29/517
摘要： A dielectric film containing ZrnullSnnullTinullO formed by atomic layer deposition using a TiI4 precursor and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Depositing titanium and oxygen onto a substrate surface by atomic layer deposition using a TiI4 precursor, depositing zirconium and oxygen onto a substrate surface by atomic layer deposition, and depositing tin and oxygen onto a substrate surface by atomic layer deposition form the ZrnullSnnullTinullO dielectric layer. Dielectric films containing ZrnullSnnullTinullO formed by atomic layer deposition using TiI4 are thermodynamically stable such that the ZrnullSnnullTinullO will have minimal reactions with a silicon substrate or other structures during processing.
摘要翻译：使用TiI4前体通过原子层沉积形成的含有Zr-Sn-Ti-O的电介质膜和制造这种电介质膜的方法产生可靠的电介质层，其具有比使用SiO 2可获得的薄的等效氧化物厚度。通过使用TiI4前体的原子层沉积将钛和氧沉积到衬底表面上，通过原子层沉积将锆和氧沉积到衬底表面上，并通过原子层沉积将锡和氧沉积到衬底表面上形成Zr-Sn-Ti -O介电层。使用TiI4通过原子层沉积形成的包含Zr-Sn-Ti-O的介电膜在热力学上是稳定的，使得Zr-Sn-Ti-O在加工过程中与硅衬底或其它结构的反应最小。

48. 发明申请

US20040110099A1 Process for forming resist pattern, semiconductor device and fabrication thereof 有权
标题翻译：用于形成抗蚀剂图案的方法，半导体器件及其制造方法
公开(公告)号：US20040110099A1
公开(公告)日：2004-06-10
申请号：US10720097
申请日：2003-11-25
申请人： FUJITSU LIMITED
发明人： Miwa Kozawa , Koji Nozaki
IPC分类号： G03C005/00 , H01L021/31
CPC分类号： H01L21/32139 , G03F7/40 , G11B5/17 , G11B5/3116 , G11B5/313 , G11B5/3163 , H01L21/0273 , H01L21/31144 , H01L21/76802 , H01L27/105 , H01L27/11526 , H01L27/11543
摘要： To thicken a resist pattern to be thickened to thereby easily form a fine pattern exceeding an exposure limit of optical source of conventional exposure devices, a process forms a resist pattern to be thickened by patterning a resist on an underlying object; applying a surfactant composition containing at least a surfactant on the resist pattern to be thickened; and applying a resist pattern thickening material containing at least a resin and a surfactant thereonto. The resist pattern to be thickened is thus thickened to form a fine pattern having a narrowed pitch.
摘要翻译：为了使要加厚的抗蚀剂图案变厚，从而容易形成超过常规曝光装置的光源的曝光极限的精细图案，工艺通过在下面的物体上图案化抗蚀剂而形成要增稠的抗蚀剂图案; 将至少含有表面活性剂的表面活性剂组合物施加到抗蚀剂图案上以使其变厚; 并涂布至少含有树脂和表面活性剂的抗蚀图形增稠材料。因此，要加厚的抗蚀剂图案被加厚以形成具有窄的间距的精细图案。

49. 发明申请

US20040102059A1 Atmospheric robot handling equipment 有权
标题翻译：大气机器人搬运设备
公开(公告)号：US20040102059A1
公开(公告)日：2004-05-27
申请号：US10303372
申请日：2002-11-25
发明人： John Dickinson
IPC分类号： H01L021/31 , H01L021/469 , H01L021/302 , H01L021/461
CPC分类号： H01L21/67778 , H01L21/67201
摘要： A semiconductor-manufacturing tool has two load locks, one for semiconductor wafers entering the tool for processing and the other for wafers leaving the tool after being processed. The load locks are of a new generation capable of being evacuated or vented in shorter times than load locks of the prior art, and permit high throughput. The tool is associated with three atmospheric wafer-handling robots to obtain the high throughput permitted by the load locks. One robot transfers wafers to be processed from a supply to a wafer pre-aligner, another robot transfers wafers from the wafer pre-aligner to the load lock for wafers entering the tool, and the third transfers processed wafers from the load lock for wafers leaving the tool back to the supply.
摘要翻译：半导体制造工具具有两个负载锁，一个用于半导体晶片进入用于处理的工具，另一个用于在处理之后离开工具的晶片。负载锁是能够在比现有技术的负载锁更短的时间内被排空或排气的新一代，并且允许高通量。该工具与三个大气晶片处理机器人相关联，以获得由加载锁允许的高吞吐量。一个机器人将要处理的晶片从供应器转移到晶片预对准器，另一个机器人将晶片从晶片预对准器传送到用于进入工具的晶片的负载锁定，并且第三个转移处理的晶片从负载锁定用于晶片离开该工具回到供应。

50. 发明申请

US20040097100A1 Semiconductor integrated circuit device and production method thereof 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20040097100A1
公开(公告)日：2004-05-20
申请号：US10477539
申请日：2003-11-13
发明人： Hidenori Sato , Katsuhiko Ichinose , Yukino Ishii , Tomoko Jinbo
IPC分类号： H01L021/31
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/452 , H01L21/02271 , H01L21/02274 , H01L21/28194 , H01L21/3185 , H01L21/76897 , H01L27/1052 , H01L27/10888 , H01L27/10894 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A CVD device (100) used for depositing a silicon nitride has a structure in which a hot wall furnace (103) for thermally degrading a source gas and a chamber (101) for forming a film over a surface of a wafer (1) are separated from each other. The hot wall furnace (103) for thermally degrading the source gas is provided above the chamber (101), and a heater (104) capable of setting the inside of the furnace at a high temperature atmosphere of approximately 1200null C. is provided at the outer periphery thereof. The source gas, supplied to the hot wall furnace (103) through pipes (105) and (106), is thermally degraded in this furnace in advance, and degraded components thereof are supplied on a stage (102) of the chamber (101) to form a film on the surface of the wafer (1).
摘要翻译：用于沉积氮化硅的CVD装置（100）具有如下结构：在晶片（1）的表面上用于使源气体热降解的热壁炉（103）和用于形成膜的室（101）彼此分离。用于使源气体热降解的热壁炉（103）设置在室（101）的上方，并且能够在大约1200℃的高温气氛下将炉内部设置的加热器（104）设置在其外围。通过管道（105）和（106）供应到热壁炉（103）的源气体预先在该炉中热劣化，并且将其劣化的组分供应到室（101）的台（102）上，以在晶片（1）的表面上形成膜。

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