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41. 发明申请

US20050164452A1 Mirror image non-volatile memory cell transistor pairs with single poly layer 审中-公开
公开(公告)号：US20050164452A1
公开(公告)日：2005-07-28
申请号：US11085387
申请日：2005-03-21
申请人： Bohumil Lojek
发明人： Bohumil Lojek
IPC分类号： G11C20060101 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11558 , G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/66825 , H01L29/7887
摘要： An arrangement of non-volatile memory transistors constructed in symmetric pairs within the space defined by intersecting pairs of word and bit lines of a memory array. The transistors have spaced apart sources and drains separated by a channel and having a floating gate over the channel characteristic of electrically erasable programmable read only memory transistors, except that there is no second poly gate. Only a single poly gate is used as a floating charge storage gate. This floating gate is placed sufficiently close to the source or drain of the device as to enable band-to-band tunneling. The floating gate is extended over the substrate to cross a word line where the floating gate is in a capacitive relation. The word line is used to program and erase the floating gate in combination with a source or drain electrode. A block erase mode is available so that the arrangement of transistors can operate as a flash memory. The single layer of poly has a T-shape, with the T-top used as the communication member with the word line and a T-base used as a floating gate. Both T-members are at the same potential. The intersecting pairs of word and bit lines resemble a tic-tac-toe pattern, with a central clear zone wherein pairs of symmetric non-volatile memory transistors are built.

42. 发明授权

US06890770B2 Magnetoresistive random access memory device structures and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件结构及其制造方法
公开(公告)号：US06890770B2
公开(公告)日：2005-05-10
申请号：US10885869
申请日：2004-07-06
申请人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
IPC分类号： G11C20060101 , G11C8/02 , H01L21/00 , H01L21/8246 , H01L27/22 , H01L29/00 , H01L29/82
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
摘要翻译：一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。操作存储元件装置形成为与第一晶体管电接触。假存储元件器件的至少一部分形成为与第二晶体管电接触。第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

43. 发明申请

US20050063235A1 PFET nonvolatile memory 有权
标题翻译： PFET非易失性存储器
公开(公告)号：US20050063235A1
公开(公告)日：2005-03-24
申请号：US10839985
申请日：2004-05-05
申请人： Alberto Pesavento , Frederic Bernard , John Hyde
发明人： Alberto Pesavento , Frederic Bernard , John Hyde
IPC分类号： G11C16/04 , G11C20060101 , G11C5/00 , G11C7/06 , G11C11/34 , G11C16/02 , G11C16/06 , G11C16/28 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/0441 , G11C16/28 , G11C2216/10 , H01L27/115 , H01L29/7883
摘要： A nonvolatile memory cell is constructed using a floating-gate pFET readout transistor having its source tied to a power source (Vdd) and its drain providing a current which can be sensed to determine the state of the cell. The gate of the pFET readout transistor provides for charge storage which can be used to represent information such as binary bits. A control capacitor structure having its first terminal coupled to a first voltage source and its second terminal coupled to the floating gate and a tunneling capacitor structure having its first terminal coupled to a second voltage source and its second terminal coupled to the floating gate are utilized in each embodiment. The control capacitor structure is fabricated so that it has much more capacitance than does the tunneling capacitor structure (and assorted stray capacitance between the floating gate and various other nodes of the cell). Manipulation of the voltages applied to the first voltage source and second voltage source (and Vdd) controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the floating gate, thus controlling the charge on the floating gate and the information value stored thereon.
摘要翻译：使用其源极连接到电源（Vdd）的浮栅pFET读出晶体管构造非易失性存储单元，其漏极提供可被感测以确定单元的状态的电流。 pFET读出晶体管的栅极提供电荷存储，可用于表示诸如二进制位之类的信息。一种控制电容器结构，其第一端耦合到第一电压源，其第二端耦合到浮置栅极，并且隧道电容器结构具有耦合到第二电压源的第一端和其耦合到浮置栅极的第二端。各实施例。制造控制电容器结构使得其具有比隧道电容器结构（以及浮动栅极和电池的各种其他节点之间的杂散电容）多得多的电容。对施加到第一电压源和第二电压源（和Vdd）的电压的操纵控制电容器结构和pFET电介质两端的电场，从而使Fowler-Nordheim将电子隧穿到浮栅上和从浮栅上，从而控制电荷浮动门和存储在其上的信息值。

44. 发明申请

US20050060512A1 Signal processing system control method and apparatus 失效
标题翻译：信号处理系统的控制方法和装置
公开(公告)号：US20050060512A1
公开(公告)日：2005-03-17
申请号：US10874637
申请日：2004-06-22
申请人： Paul Underbrink , Henry Falk
发明人： Paul Underbrink , Henry Falk
IPC分类号： G06F12/00 , G11C20060101
CPC分类号： G01S19/37
摘要： A signal processing system control method and apparatus are described. Various embodiments include a signal processing system with multiple subsystems. A method for controlling the signal processing system includes storing channel records in a designated area of shared memory. A channel records include channel data which includes one of multiple discrete signals to be processed by multiple subsystems in a time-multiplexed manner. The channel record includes information used by the multiple subsystems to process a channel, including information used to configure the multiple subsystems, information used to allocate the shared memory, and information used to communicate between multiple subsystems.
摘要翻译：描述信号处理系统控制方法和装置。各种实施例包括具有多个子系统的信号处理系统。用于控制信号处理系统的方法包括将频道记录存储在共享存储器的指定区域中。信道记录包括信道数据，其包括多个子系统以时间复用方式处理的多个离散信号之一。信道记录包括多个子系统用于处理信道的信息，包括用于配置多个子系统的信息，用于分配共享存储器的信息，以及用于在多个子系统之间进行通信的信息。

45. 发明授权

US06858442B2 Ferroelectric memory integrated circuit with improved reliability 失效
标题翻译：铁电存储器集成电路具有改进的可靠性
公开(公告)号：US06858442B2
公开(公告)日：2005-02-22
申请号：US10248861
申请日：2003-02-25
申请人： Andreas Hilliger , Uwe Wellhausen
发明人： Andreas Hilliger , Uwe Wellhausen
IPC分类号： G11C20060101 , G11C11/22 , H01L21/00 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L21/8142
CPC分类号： H01L28/55 , G11C11/22 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11502 , H01L28/65 , H01L28/75
摘要： A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.
摘要翻译：描述了具有电介质层的具有电介质层的电容器的存储单元。底部电极通过底部电极插塞耦合到晶体管的第一扩散区域。电介质层覆盖电容器。电介质层之上是第一阻挡层。在其中形成有插塞以耦合到第二扩散区域的电介质层中形成通孔。通孔包括基本垂直的侧壁。第二阻挡层对通孔的侧壁进行排列。然后将导电材料沉积在衬底上，填充通孔以形成插头。通过设置第一和第二阻挡层，可以减小可能不利地影响电容器的氢的扩散，从而提高可靠性。

46. 发明申请

US20050018474A1 SRAM cell structure and circuits 失效
标题翻译： SRAM单元结构和电路
公开(公告)号：US20050018474A1
公开(公告)日：2005-01-27
申请号：US10883581
申请日：2004-06-30
申请人： Jeong-Duk Sohn
发明人： Jeong-Duk Sohn
IPC分类号： G11C20060101 , G11C11/00 , G11C11/413 , G11C11/419
CPC分类号： G11C11/419
摘要： An SRAM circuit structure and method for reducing leakage currents and/or increasing the speed of the devices. Various forms of SRAM devices may be fabricated utilizing the techniques, such as single port and dual port RAM devices. By way of example the SRAM structure utilizes separate write and read lines, splits the circuit into portions which can benefit from having differing threshold levels, and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor. The structure is particularly well suited for forming transistors in a combination of NMOS and PMOS, or solely in NMOS. Memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated.
摘要翻译：一种用于减少漏电流和/或提高器件速度的SRAM电路结构和方法。可以使用诸如单端口和双端口RAM器件的技术来制造各种形式的SRAM器件。作为示例，SRAM结构使用单独的写入和读取线，将电路分成可以受益于具有不同阈值电平的部分，并且可以允许分离读取路径晶体管用于连接到连接到源极晶体管的第一端子和虚拟节点。该结构特别适用于在NMOS和PMOS的组合中形成晶体管，或者仅在NMOS中。存储器阵列可以根据本发明以多个不同的分布式或集中布置来组织，其中参考读取路径和感测块是共享的或专用的。

47. 发明申请

US20050012119A1 Method for making high density nonvolatile memory 有权
公开(公告)号：US20050012119A1
公开(公告)日：2005-01-20
申请号：US10855784
申请日：2004-05-26
申请人： S. Herner , Maitreyee Mahajani
发明人： S. Herner , Maitreyee Mahajani
IPC分类号： G11C20060101 , G11C5/02 , H01L21/00 , H01L21/331 , H01L21/82 , H01L21/8238 , H01L23/48 , H01L27/102 , H01L27/148 , H01L29/94 , H01L31/0392 , H01L31/119
CPC分类号： G11C5/02 , H01L21/8238 , H01L23/48 , H01L27/1021 , H01L27/148 , H01L29/94 , H01L2924/0002 , H01L2924/00
摘要： An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

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