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1. 发明申请

US20060151819A1 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US20060151819A1
公开(公告)日：2006-07-13
申请号：US11373080
申请日：2006-03-09
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬层，并且蚀刻用于V0接触的孔，直到蚀刻被衬垫层停止。

2. 发明申请

US20050013091A1 MULTI-LAYER BARRIER ALLOWING RECOVERY ANNEAL FOR FERROELECTRIC CAPACITORS 有权
标题翻译：多层障碍物允许用于电容电容器的恢复电极
公开(公告)号：US20050013091A1
公开(公告)日：2005-01-20
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

3. 发明授权

US07378700B2 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US07378700B2
公开(公告)日：2008-05-27
申请号：US11373080
申请日：2006-03-09
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/76
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬层，并且蚀刻用于V0接触的孔，直到蚀刻被衬垫层停止。

4. 发明授权

US06946735B2 Side-wall barrier structure and method of fabrication 有权
标题翻译：侧壁屏障结构及其制造方法
公开(公告)号：US06946735B2
公开(公告)日：2005-09-20
申请号：US10307257
申请日：2002-11-29
申请人： Stefan Gernhardt , Jenny Lian , Andreas Hilliger , Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel
发明人： Stefan Gernhardt , Jenny Lian , Andreas Hilliger , Rainer Bruchhaus , Uwe Wellhausen , Nicolas Nagel
IPC分类号： H01L21/02 , H01L21/768 , H01L23/48
CPC分类号： H01L21/7687 , H01L21/76877 , H01L28/60
摘要： The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.
摘要翻译：本发明包括具有通过CP接触的多硅插头的晶片。多晶硅插头由相对高掺杂的多晶硅层和相对轻掺杂的多晶硅层形成。相对轻掺杂的多晶硅层通过相对重掺杂的多晶硅层延伸超过相对重掺杂的多晶硅层朝向晶片的表面。阻挡层覆盖相对较轻掺杂的多晶硅层的顶壁和侧壁，用于减少多晶硅插头表面的氧化。通过在CP接触中沉积相对重掺杂的多晶硅层来制造晶片，沉积相对轻掺杂的多晶硅层以通过相对重掺杂的多晶硅层，以及沉积阻挡层以覆盖顶部和侧壁相对轻掺杂的多晶硅层，以减少在多晶硅塞的表面处的氧化。

5. 发明申请

US20050082583A1 Self-aligned Vo-contact for cell size reduction 失效
标题翻译：自对准Vo接触，以减小电池尺寸
公开(公告)号：US20050082583A1
公开(公告)日：2005-04-21
申请号：US10677852
申请日：2003-10-01
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L21/02 , H01L21/60 , H01L29/76
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬垫层，并且蚀刻用于VO触点的孔，直到蚀刻被衬垫层停止。

6. 发明授权

US07101785B2 Formation of a contact in a device, and the device including the contact 有权
标题翻译：在设备中形成联系人，以及包括联系人的设备
公开(公告)号：US07101785B2
公开(公告)日：2006-09-05
申请号：US10625483
申请日：2003-07-22
申请人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
发明人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76831 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.
摘要翻译：与器件的底层形成接触的方法包括以下步骤：形成接触孔，在器件的接触孔中形成阻挡材料的接触孔阻挡层，蚀刻位于接触孔底面的接触孔阻挡层接触孔，将衬垫材料沉积在接触孔中，并用导电材料填充接触孔。根据该方法形成诸如半导体，无源器件，电容器或FeRAM的器件。接触孔的侧壁上的接触孔阻挡层的部分阻止氢和/或氧的横向扩散。接触孔阻挡层可以在湿蚀刻工艺之后进行，以填充由该工艺引起的现有阻挡层中的空隙，或者在湿蚀刻工艺之前，以防止对现有阻挡层的损坏。

7. 发明授权

US07061035B2 Self-aligned V0-contact for cell size reduction 失效
标题翻译：自对准V0接触用于电池尺寸减小
公开(公告)号：US07061035B2
公开(公告)日：2006-06-13
申请号：US10677852
申请日：2003-10-01
申请人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
发明人： Jingyu Lian , Nicolas Nagel , Stefan Gernhardt , Rainer Bruchhaus , Andreas Hilliger , Uwe Wellhausen
IPC分类号： H01L29/94
CPC分类号： H01L21/76897 , H01L28/55
摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the VO-contact until the etching is stopped by the liner layer.
摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。使用底部电极对齐V0触点。衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬垫层，并且蚀刻用于VO触点的孔，直到蚀刻被衬垫层停止。

8. 发明授权

US06839220B1 Multi-layer barrier allowing recovery anneal for ferroelectric capacitors 有权
标题翻译：用于铁电电容器的多层屏障允许恢复退火
公开(公告)号：US06839220B1
公开(公告)日：2005-01-04
申请号：US10623461
申请日：2003-07-18
申请人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
发明人： Andreas Hilliger , Jingyu Lian , Nicolas Nagel , Rainer Bruchhaus , Stefan Gernhardt , Uwe Wellhausen , Bum-Ki Moon , Karl Hornik
IPC分类号： H01G4/06 , H01G4/12 , H01G4/33 , H01L21/02 , H01L21/8246 , H01L27/115
CPC分类号： H01G4/1245 , H01G4/33 , H01L28/57
摘要： A multi-layer barrier for a ferroelectric capacitor includes an outdiffusion barrier layer permeable to both hydrogen and oxygen. The outdiffusion barrier layer covers the ferroelectric of the capacitor. Oxygen passes through the outdiffusion barrier layer into the ferroelectric during an oxygen anneal in order to repair damage to the ferroelectric caused during etching. The outdiffusion barrier layer reduces the decomposition of the ferroelectric by blocking molecules leaving the ferroelectric during the oxygen anneal. The multi-layer barrier also includes a hydrogen barrier layer deposited on the outdiffusion barrier layer after repair of the ferroelectric by the oxygen anneal. The hydrogen barrier layer allows the multi-layer barrier to block the passage of hydrogen into the ferroelectric during back-end processes.
摘要翻译：用于铁电电容器的多层屏障包括可渗透氢和氧的扩散阻挡层。外扩散阻挡层覆盖电容器的铁电体。在氧退火期间，氧气通过外扩散阻挡层进入铁电体，以便修复在蚀刻期间引起的铁电体损坏。扩散阻挡层通过在氧退火期间阻挡离开铁电体的分子来减少铁电体的分解。多层屏障还包括通过氧退火修复铁电体之后沉积在扩散阻挡层上的氢阻挡层。氢阻挡层允许多层屏障在后端工艺期间阻止氢气进入铁电体。

9. 发明授权

US06858442B2 Ferroelectric memory integrated circuit with improved reliability 失效
标题翻译：铁电存储器集成电路具有改进的可靠性
公开(公告)号：US06858442B2
公开(公告)日：2005-02-22
申请号：US10248861
申请日：2003-02-25
申请人： Andreas Hilliger , Uwe Wellhausen
发明人： Andreas Hilliger , Uwe Wellhausen
IPC分类号： G11C20060101 , G11C11/22 , H01L21/00 , H01L21/02 , H01L21/768 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L21/8142
CPC分类号： H01L28/55 , G11C11/22 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L27/11502 , H01L28/65 , H01L28/75
摘要： A memory cell having capacitor with top and bottom electrodes with a dielectric layer between is described. The bottom electrode is coupled to a first diffusion region of a transistor by a bottom electrode plug. A dielectric layer covers the capacitor. Above the dielectric layer is a first barrier layer. A via is created in the dielectric layer in which a plug is formed to couple to the second diffusion region. The via comprises substantially vertical sidewalls. A second barrier layer lines the sidewalls of the via. A conductive material is then deposited on the substrate, filling the via to form the plug. By providing the first and second barrier layers, the diffusion of hydrogen which can adversely impact the capacitor is reduced, thereby improving the reliability.
摘要翻译：描述了具有电介质层的具有电介质层的电容器的存储单元。底部电极通过底部电极插塞耦合到晶体管的第一扩散区域。电介质层覆盖电容器。电介质层之上是第一阻挡层。在其中形成有插塞以耦合到第二扩散区域的电介质层中形成通孔。通孔包括基本垂直的侧壁。第二阻挡层对通孔的侧壁进行排列。然后将导电材料沉积在衬底上，填充通孔以形成插头。通过设置第一和第二阻挡层，可以减小可能不利地影响电容器的氢的扩散，从而提高可靠性。

10. 发明申请

US20050020054A1 Formation of a contact in a device, and the device including the contact 有权
标题翻译：在设备中形成联系人，以及包括联系人的设备
公开(公告)号：US20050020054A1
公开(公告)日：2005-01-27
申请号：US10625483
申请日：2003-07-22
申请人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
发明人： Andreas Hilliger , Stefan Gernhardt , Uwe Wellhausen , Karl Hornik
IPC分类号： H01L21/02 , H01L21/768 , H01L23/522 , H01L27/115 , H01L21/4763
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76831 , H01L27/11502 , H01L28/57 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a contact to an underlayer of a device includes the steps of forming a contact hole, forming a contact hole barrier layer of a barrier material in the contact hole of the device, etching the contact hole barrier layer on the bottom surface of the contact hole, depositing a liner material in the contact hole, and filling the contact hole with a conductive material. A device such as a semiconductor, passive device, capacitor or FeRAM is formed in accordance with the method. The portions of the contact hole barrier layer on the side walls of the contact hole inhibit lateral diffusion of hydrogen and/or oxygen. The contact hole barrier layer can be performed after a wet etch process to fill voids in an existing barrier layer caused by that process, or prior to the wet etch process to prevent damage to the existing barrier layer.
摘要翻译：与器件的底层形成接触的方法包括以下步骤：形成接触孔，在器件的接触孔中形成阻挡材料的接触孔阻挡层，蚀刻位于接触孔底面的接触孔阻挡层接触孔，将衬垫材料沉积在接触孔中，并用导电材料填充接触孔。根据该方法形成诸如半导体，无源器件，电容器或FeRAM的器件。接触孔的侧壁上的接触孔阻挡层的部分阻止氢和/或氧的横向扩散。接触孔阻挡层可以在湿蚀刻工艺之后进行，以填充由该工艺引起的现有阻挡层中的空隙，或者在湿蚀刻工艺之前，以防止对现有阻挡层的损坏。

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