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41. 发明授权

US08441299B2 Dual path level shifter 有权
公开(公告)号：US08441299B2
公开(公告)日：2013-05-14
申请号：US12657857
申请日：2010-01-28
申请人： Chris Olson , Neil Calanca
发明人： Chris Olson , Neil Calanca
IPC分类号： H03L5/00
CPC分类号： H03K19/018592 , H03K19/017509 , H03K19/018521
摘要： Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters.

42. 发明申请

US20120161811A1 DRIVER CIRCUIT CORRECTION ARM DECOUPLING RESISTANCE IN STEADY STATE MODE 有权
标题翻译：驱动电路校正ARM在稳态模式下的解耦电阻
公开(公告)号：US20120161811A1
公开(公告)日：2012-06-28
申请号：US12979336
申请日：2010-12-28
申请人： Rajavelu Thinakaran , Ashwin Ramachandran
发明人： Rajavelu Thinakaran , Ashwin Ramachandran
IPC分类号： H03K19/003
CPC分类号： H03K19/018571 , H03K19/01707 , H03K19/018585 , H03K19/018592 , H04L25/03834
摘要： A voltage-mode driver circuit supporting pre-emphasis is implemented to include a driver arm and a correction arm. The driver arm receives an input signal, and is operable, in pre-emphasis intervals as well as steady-state intervals, to connect a first impedance between an output terminal of the driver circuit and a constant reference potential. The correction arm is operable to connect a correction impedance in parallel with the first impedance in pre-emphasis intervals, and to decouple the correction impedance from the first impedance in steady-state intervals. The parallel connection of the first impedance and the correction impedance in pre-emphasis intervals increases the voltage level of the output signal of the driver circuit in pre-emphasis intervals. The use of the correction arm compensates for the effect of parasitic capacitance at one or more nodes of the driver circuit, thereby reducing the settling time of the output signal and enabling high-speed operation.
摘要翻译：实施支持预加重的电压模式驱动电路，以包括驱动器臂和校正臂。驱动器臂接收输入信号，并且可在预加重间隔以及稳态间隔中操作，以连接驱动电路的输出端和恒定参考电位之间的第一阻抗。校正臂可操作以在预加重间隔中与第一阻抗平行地连接校正阻抗，并且在稳态间隔中将校正阻抗与第一阻抗分离。在预加重间隔中，第一阻抗和校正阻抗的并联连接以预加重间隔增加驱动器电路的输出信号的电压电平。校正臂的使用补偿了驱动器电路的一个或多个节点处的寄生电容的影响，从而减小了输出信号的建立时间并实现了高速操作。

43. 发明申请

US20110181338A1 Dual path level shifter 有权
标题翻译：双路电平转换器
公开(公告)号：US20110181338A1
公开(公告)日：2011-07-28
申请号：US12657857
申请日：2010-01-28
申请人： Chris Olson , Neil Calanca
发明人： Chris Olson , Neil Calanca
IPC分类号： H03L5/00
CPC分类号： H03K19/018592 , H03K19/017509 , H03K19/018521
摘要： Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters.
摘要翻译：描述双路径电平移位器的方法和装置。所描述的电平移位器装置可以包括电压 - 电流和电流 - 电压转换器。

44. 发明授权

US07902873B2 Semiconductor chip and semiconductor device 有权
标题翻译：半导体芯片和半导体器件
公开(公告)号：US07902873B2
公开(公告)日：2011-03-08
申请号：US11561567
申请日：2006-11-20
申请人： Tomoaki Isozaki
发明人： Tomoaki Isozaki
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/018592 , H01L25/07 , H01L27/092 , H01L29/78 , H01L2924/0002 , H03K3/038 , H03K19/018521 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.
摘要翻译：半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。根据本发明的半导体芯片方便地用于制造半导体器件。第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。输出电路将信号输出到第一外部输出端子。第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。与在不同工作电压下工作的多个半导体芯片相互连接并将其用于半导体器件的情况相比，整个芯片面积减小，该半导体器件具有以不同于各个工作电压的电压工作的输入/输出缓冲器导致芯片面积增加。

45. 发明申请

US20100277217A1 INPUT/OUTPUT SIGNAL CONTROLLER 有权
标题翻译：输入/输出信号控制器
公开(公告)号：US20100277217A1
公开(公告)日：2010-11-04
申请号：US12811771
申请日：2008-07-15
申请人： Mitsuo Takarada
发明人： Mitsuo Takarada
IPC分类号： H03K17/56 , H03K17/687
CPC分类号： H04L5/1415 , H03K19/018592 , H04B2203/5445 , H04B2203/547 , H04L25/0272 , H04L25/0298
摘要： To easily judge a transmission signal outputted from an own electronic device. A transmission part 7 outputs a transmission signal to a transmission path 1 side. Switching parts Q1 and Q2 are connected between a constant voltage power source and the transmission path 1, to switch on/off of a signal supplied from the constant voltage power source, being the transmission signal from the transmission part 7, and output it to the transmission path 1. A reception part 9 receives the transmission signal from the transmission path 1. A detection part 13 is connected between the constant voltage power source and the switching parts Q1, Q2, to detect the transmission signal from the transmission part 7 flowing through the switching parts Q1 and Q2. A selection part 15 selects the reception part 9, when the transmission signal from the transmission part 7 is not detected by the detection part 13.
摘要翻译：容易地判断从自己的电子设备输出的发送信号。发送部7向发送路径1侧输出发送信号。开关部分Q1和Q2连接在恒压电源和传输路径1之间，以将来自恒压电源的信号作为来自发送部分7的发送信号的接通/断开，并将其输出到传输路径1.接收部分9从传输路径1接收传输信号。检测部分13连接在恒压电源和开关部分Q1，Q2之间，以检测来自传输部分7的传输信号开关部分Q1和Q2。当来自发送部分7的发送信号未被检测部分13检测到时，选择部分15选择接收部分9。

46. 发明授权

US07768299B2 Voltage tolerant floating N-well circuit 有权
标题翻译：耐压漂浮N阱电路
公开(公告)号：US07768299B2
公开(公告)日：2010-08-03
申请号：US11832128
申请日：2007-08-01
申请人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00384
摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
摘要翻译：提出了用于耐压漂浮N阱电路的方法和装置。提供了一种用于减轻由输入电压引起的漏电流的装置，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。该装置还可以包括耦合到负电压源和第一晶体管的可控下拉通路，其中可控下拉通道被配置为在第一状态期间导通第一晶体管并上拉浮动节点。该装置还可以包括具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极的第二晶体管，其中第二晶体管被配置为在第二状态期间将浮动节点置于浮动电位。

47. 发明授权

US07755412B2 Bi-directional level shifted interrupt control 失效
标题翻译：双向电平移位中断控制
公开(公告)号：US07755412B2
公开(公告)日：2010-07-13
申请号：US12060561
申请日：2008-04-01
申请人： Jeffrey M. Thoma
发明人： Jeffrey M. Thoma
IPC分类号： H03L5/00
CPC分类号： H03K19/018557 , H03K19/018592
摘要： The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one “read only” and another “input/output” pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin.
摘要翻译：本示例提供了提供可由不同电压供电并且可以在不同逻辑电平下操作的电路之间的互操作性的电路。可以从由晶体管电路提供的阻抗提供隔离，并且电平移位可以由分压网络提供。因此，示例性从机和主机（或等效地两个正在耦合在一起的电路）可以在不同的电压上工作。这可能是有用的，因为诸如处理器的一些电路可能需要比寻求耦合在一起的其它处理器更高或更低的电压。该电路还可能需要一个“只读”引脚和另一个“输入/输出”引脚，因此减少了实现电路功能所需的资源。本示例对于可以使用用于通信协议的软件算法的微处理器可能是有用的，当利用一个输入/输出引脚和一个仅输入引脚时，可以实现这些算法。

48. 发明授权

US07639045B2 Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback 失效
标题翻译：用于双向缓冲的双向缓冲器和方法，可减少由于反馈引起的毛刺
公开(公告)号：US07639045B2
公开(公告)日：2009-12-29
申请号：US12177736
申请日：2008-07-22
申请人： Ali Motamed , Subrat Mohapatra
发明人： Ali Motamed , Subrat Mohapatra
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00315
摘要： A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.
摘要翻译：双向缓冲器至少包括第一和第二对单触发和晶体管。至少第一对单触发器和第一对晶体管使第二输入/输出（I / O）端子跟随第一I / O端子。至少第二对单触发器和第二对晶体管使得第一I / O端子能够跟随第二I / O端子。检测信号的方向是从第一个I / O端子到第二个I / O端子，反之亦然。如果方向是从第一I / O端子到第二I / O端子，则至少暂时禁用第二对一对一个，从而减少可能从第二I / O端子到第一I / O端子发生的反馈 I / O端子。如果方向是从第二I / O端子到第一I / O端子，则至少暂时禁用第一对一对一个，从而减少可能从第一I / O端子到第二I / O端子发生的反馈 I / O端子。

49. 发明申请

US20090289693A1 BI-DIRECTIONAL BUFFER AND METHOD FOR BI-DIRECTIONAL BUFFERING THAT REDUCE GLITCHES DUE TO FEEDBACK 失效
标题翻译：双向缓冲器和双向方向缓冲的方法，减少反馈引起的反应
公开(公告)号：US20090289693A1
公开(公告)日：2009-11-26
申请号：US12177736
申请日：2008-07-22
申请人： Ali Motamed , Subrat Mohapatra
发明人： Ali Motamed , Subrat Mohapatra
IPC分类号： H03K17/687
CPC分类号： H03K19/018592 , H03K19/00315
摘要： A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.
摘要翻译：双向缓冲器至少包括第一和第二对单触发和晶体管。至少第一对单触发器和第一对晶体管使第二输入/输出（I / O）端子跟随第一I / O端子。至少第二对单触发器和第二对晶体管使得第一I / O端子能够跟随第二I / O端子。检测信号的方向是从第一个I / O端子到第二个I / O端子，反之亦然。如果方向是从第一I / O端子到第二I / O端子，则至少暂时禁用第二对一对一个，从而减少可能从第二I / O端子到第一I / O端子发生的反馈 I / O端子。如果方向是从第二I / O端子到第一I / O端子，则至少暂时禁用第一对一对一个，从而减少可能从第一I / O端子到第二I / O端子发生的反馈 I / O端子。

50. 发明申请

US20080164932A1 Semi-buffered auto-direction-sensing voltage translator 有权
标题翻译：半缓冲自动方向感应电压转换器
公开(公告)号：US20080164932A1
公开(公告)日：2008-07-10
申请号：US11901054
申请日：2007-09-14
申请人： Mark Benjamin Welty
发明人： Mark Benjamin Welty
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03K19/018585 , H03K19/018592
摘要： In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bidirectional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.
摘要翻译：在用于将电压电平转换为接口电子装置的方法和系统中，电压转换器可操作以根据开漏工作模式并根据电压转换器执行在电子装置之间交换的双向信号的电压电平的平移推挽操作模式。电压转换器包括用于检测信号转换的边沿速率加速器，并且包括可配置电阻器以提供直流（DC）驱动电流和DC偏置以保持期望的电压电平。电压转换器可在开漏模式下操作以检测电子设备的存在，并且在检测到电子设备时可在推挽模式下操作。

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