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1. 发明授权

US08138814B2 High signal level compliant input/output circuits 有权
标题翻译：高信号电平兼容输入/输出电路
公开(公告)号：US08138814B2
公开(公告)日：2012-03-20
申请号：US12181655
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K19/017581 , H03K19/018507
摘要： A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.
摘要翻译：用于接口电路的信号驱动器具有第一级电平移位器，以接收输入信号并以第一信号电平输出信号。信号驱动器还具有耦合到第一级电平移位器的第二级电平移位器，以在第二信号电平输出信号。第一级和第二级电平移位器的电子部件具有小于第二信号电平的可靠性限制。第一级电平移位器和第二级电平转换器的第一和第二级配置防止当处理用于在第二信号电平输出的信号时将电子部件暴露于高于可靠性限制的端对端信号电平。

2. 发明授权

US07804334B2 High signal level compliant input/output circuits 有权
标题翻译：高信号电平兼容输入/输出电路
公开(公告)号：US07804334B2
公开(公告)日：2010-09-28
申请号：US12181633
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03K5/22
CPC分类号： H03K19/018507 , G01R19/16519 , G01R19/16552 , H03K19/00315
摘要： A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.
摘要翻译：电平检测器具有适于接收用于检测特定电平的多个信号电平的信号的输入电路。信号电平包括第一信号电平和较大的第二信号电平。输入电路的电子元件具有小于第二信号电平的可靠性水平。锁存电路耦合到输入电路，用于锁存与所接收信号的检测电平一致的信号。

3. 发明授权

US07768299B2 Voltage tolerant floating N-well circuit 有权
标题翻译：耐压漂浮N阱电路
公开(公告)号：US07768299B2
公开(公告)日：2010-08-03
申请号：US11832128
申请日：2007-08-01
申请人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03K19/0175
CPC分类号： H03K19/018592 , H03K19/00384
摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.
摘要翻译：提出了用于耐压漂浮N阱电路的方法和装置。提供了一种用于减轻由输入电压引起的漏电流的装置，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。该装置还可以包括耦合到负电压源和第一晶体管的可控下拉通路，其中可控下拉通道被配置为在第一状态期间导通第一晶体管并上拉浮动节点。该装置还可以包括具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极的第二晶体管，其中第二晶体管被配置为在第二状态期间将浮动节点置于浮动电位。

4. 发明申请

US20100026362A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 有权
标题翻译：高信号电平输入/输出电路
公开(公告)号：US20100026362A1
公开(公告)日：2010-02-04
申请号：US12181633
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/018507 , G01R19/16519 , G01R19/16552 , H03K19/00315
摘要： A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.
摘要翻译：电平检测器具有适于接收用于检测特定电平的多个信号电平的信号的输入电路。信号电平包括第一信号电平和较大的第二信号电平。输入电路的电子元件具有小于第二信号电平的可靠性水平。锁存电路耦合到输入电路，用于锁存与所接收信号的检测电平一致的信号。

5. 发明授权

US08593203B2 High signal level compliant input/output circuits 有权
标题翻译：高信号电平兼容输入/输出电路
公开(公告)号：US08593203B2
公开(公告)日：2013-11-26
申请号：US12181672
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K19/018507 , H03K19/018585
摘要： An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.
摘要翻译：接口输入具有适于接收高于主机电路的电子部件可以可靠地处理的最大信号电平的输入信号电平的输入电路。输入电路将输入信号的电平移动到期望的信号电平。保持器电路耦合到输入电路，并保持与输入信号电平一致的移位信号的触发电平。

6. 发明授权

US08106699B2 High signal level compliant input/output circuits 有权
标题翻译：高信号电平兼容输入/输出电路
公开(公告)号：US08106699B2
公开(公告)日：2012-01-31
申请号：US12181645
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K19/018507
摘要： A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.
摘要翻译：电平移位器具有上拉或下拉电路中的至少一个。该电路由可靠性限制小于电平转换器输出的最大信号电平的电子元件组成。电平移位器还具有耦合到上拉或下拉电路中的至少一个的定时电路。定时电路控制将输入信号施加到上拉或下拉电路中的至少一个的时间，以防止电子部件经受的终端信号电平超过可靠性限制。

7. 发明申请

US20100026363A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 有权
标题翻译：高信号电平输入/输出电路
公开(公告)号：US20100026363A1
公开(公告)日：2010-02-04
申请号：US12181645
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K19/018507
摘要： A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.
摘要翻译：电平移位器具有上拉或下拉电路中的至少一个。该电路由可靠性限制小于电平转换器输出的最大信号电平的电子元件组成。电平移位器还具有耦合到上拉或下拉电路中的至少一个的定时电路。定时电路控制将输入信号施加到上拉或下拉电路中的至少一个的时间，以防止电子部件经受的终端信号电平超过可靠性限制。

8. 发明授权

US07772887B2 High signal level compliant input/output circuits 有权
标题翻译：高信号电平兼容输入/输出电路
公开(公告)号：US07772887B2
公开(公告)日：2010-08-10
申请号：US12181621
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03K19/0175 , G06F13/36
CPC分类号： G06F13/4072 , G06F13/385
摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.
摘要翻译：信号接口电路具有用于将主机电路通信耦合到多个外围设备的外围电路的信号路径。信号路径中的通信信号为周边信号电平。信号路径具有适于在主机电路和外围电路之间传送信号的电子部件。信号路径中的电子元件具有小于外围信号电平的可靠性限制。信号路径中的电子部件的配置允许以外围信号电平进行信号的通信。

9. 发明申请

US20100030924A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 有权
标题翻译：高信号电平输入/输出电路
公开(公告)号：US20100030924A1
公开(公告)日：2010-02-04
申请号：US12181621
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： G06F3/00
CPC分类号： G06F13/4072 , G06F13/385
摘要： A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.
摘要翻译：信号接口电路具有用于将主机电路通信耦合到多个外围设备的外围电路的信号路径。信号路径中的通信信号为周边信号电平。信号路径具有适于在主机电路和外围电路之间传送信号的电子部件。信号路径中的电子元件具有小于外围信号电平的可靠性限制。信号路径中的电子部件的配置允许以外围信号电平进行信号的通信。

10. 发明申请

US20100026364A1 HIGH SIGNAL LEVEL COMPLIANT INPUT/OUTPUT CIRCUITS 有权
标题翻译：高信号电平输入/输出电路
公开(公告)号：US20100026364A1
公开(公告)日：2010-02-04
申请号：US12181672
申请日：2008-07-29
申请人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
发明人： Vijay Shankar , Abheek Gupta , Vaishnav Srinivas , Vivek Mohan
IPC分类号： H03L5/00
CPC分类号： H03K19/00315 , H03K19/018507 , H03K19/018585
摘要： An interface input has an input circuit adapted to receive input signal levels higher than a maximum signal level that a host circuitry's electronic components can reliably handle. The input circuit shifts the level of the input signal to a desired signal level. A keeper circuit is coupled to the input circuit and maintains trigger levels of the shifted signals consistent with the input signal level.
摘要翻译：接口输入具有适于接收高于主机电路的电子部件可以可靠地处理的最大信号电平的输入信号电平的输入电路。输入电路将输入信号的电平移动到期望的信号电平。保持器电路耦合到输入电路，并保持与输入信号电平一致的移位信号的触发电平。

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