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1. 发明授权

US08350593B2 Semiconductor chip and semiconductor device 有权
标题翻译：半导体芯片和半导体器件
公开(公告)号：US08350593B2
公开(公告)日：2013-01-08
申请号：US13015246
申请日：2011-01-27
申请人： Tomoaki Isozaki
发明人： Tomoaki Isozaki
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/018592 , H01L25/07 , H01L27/092 , H01L29/78 , H01L2924/0002 , H03K3/038 , H03K19/018521 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.
摘要翻译：半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。根据本发明的半导体芯片方便地用于制造半导体器件。第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。输出电路将信号输出到第一外部输出端子。第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。与在不同工作电压下工作的多个半导体芯片相互连接并将其用于半导体器件的情况相比，整个芯片面积减小，该半导体器件具有以不同于各个工作电压的电压工作的输入/输出缓冲器导致芯片面积增加。

2. 发明授权

US07400134B2 Integrated circuit device with multiple chips in one package 有权
标题翻译：具有多个芯片的集成电路器件在一个封装中
公开(公告)号：US07400134B2
公开(公告)日：2008-07-15
申请号：US11036980
申请日：2005-01-19
申请人： Yoshiaki Morishita , Nobuteru Oh , Tomoaki Isozaki
发明人： Yoshiaki Morishita , Nobuteru Oh , Tomoaki Isozaki
IPC分类号： H01L23/48 , H01L29/10
CPC分类号： G11C29/1201 , G01R31/31701 , G01R31/31723 , G11C29/48 , G11C2029/0401 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2225/06513 , H01L2225/06596 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2224/05599
摘要： The integrated circuit device includes a memory chip and a logic chip. The memory chip has memory I/O pads and test pads. The test pads are placed in line at the position outer than memory I/O pads and larger than the memory I/O pads. The logic chip has logic COC I/O pads. The logic COC I/O pads are connected to the memory I/O pads.
摘要翻译：集成电路装置包括存储芯片和逻辑芯片。存储器芯片具有存储器I / O焊盘和测试焊盘。测试焊盘放置在比存储器I / O焊盘外部的位置并且大于存储器I / O焊盘的位置。逻辑芯片具有逻辑COC I / O焊盘。逻辑COC I / O焊盘连接到存储器I / O焊盘。

3. 发明申请

US20060050454A1 Chip-on-chip type semiconductor device 审中-公开
标题翻译：芯片片式半导体器件
公开(公告)号：US20060050454A1
公开(公告)日：2006-03-09
申请号：US11218584
申请日：2005-09-06
申请人： Kazuhiro Koudate , Tomoaki Isozaki
发明人： Kazuhiro Koudate , Tomoaki Isozaki
IPC分类号： H02H9/00
CPC分类号： H01L25/0657 , H01L23/60 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/32145 , H01L2224/48465 , H01L2224/73204 , H01L2224/73207 , H01L2225/0651 , H01L2225/06513 , H01L2225/06582 , H01L2924/00014 , H01L2924/13091 , H03K19/018521 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A chip-on-chip semiconductor device is composed of: a first chip operating on a first power supply voltage; and a second chip operating on a second power supply voltage lower than the first power supply voltage, the first and second chips being flip-chip connected through inter-chip connection bumps. The second chip is designed to provide level-conversion for a transmission signal received from the first chip.
摘要翻译：片上芯片半导体器件由以下部分组成：第一芯片，其工作在第一电源电压上; 以及在低于第一电源电压的第二电源电压上工作的第二芯片，第一芯片和第二芯片通过芯片间连接凸块倒装芯片连接。第二芯片被设计成为从第一芯片接收的发送信号提供电平转换。

4. 发明授权

US4805508A Sound synthesizing circuit 失效
标题翻译：声合成电路
公开(公告)号：US4805508A
公开(公告)日：1989-02-21
申请号：US77546
申请日：1987-07-24
申请人： Tomoaki Isozaki
发明人： Tomoaki Isozaki
IPC分类号： G10H7/00 , G10H5/06 , G10H7/04 , G10H1/00
CPC分类号： G10H5/06 , G10H7/04 , Y10S84/11
摘要： A sound synthesizing circuit has means for synthesizing sound digital data in a pitch period of a sound to be synthesized and means for producing a sound analog signal according to the synthesized sound digital data. The synthesized sound digital data are sequentially transferred to the producing means according to a sequential sampling pulse. The sequential sampling pulse has a predetermined interval and a corrected interval different from the predetermined interval in one pitch period of a sound to be synthesized. Thus, a sound of good quality with an arbitrary interval can be synthesized in a wide scale by a simple hardware integrated circuit in a small semiconductor chip.
摘要翻译：声音合成电路具有用于在要合成的声音的音调周期中合成声音数字数据的装置和根据合成声音数字数据产生声音模拟信号的装置。合成声音数字数据根据顺序采样脉冲依次传送到产生装置。顺序采样脉冲具有预定的间隔和与要合成的声音的一个音调周期中的预定间隔不同的校正间隔。因此，通过在小型半导体芯片中的简单硬件集成电路，可以大范围地合成具有任意间隔的良好质量的声音。

5. 发明授权

US07902873B2 Semiconductor chip and semiconductor device 有权
标题翻译：半导体芯片和半导体器件
公开(公告)号：US07902873B2
公开(公告)日：2011-03-08
申请号：US11561567
申请日：2006-11-20
申请人： Tomoaki Isozaki
发明人： Tomoaki Isozaki
IPC分类号： H03K19/0175 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/018592 , H01L25/07 , H01L27/092 , H01L29/78 , H01L2924/0002 , H03K3/038 , H03K19/018521 , H01L2924/00
摘要： A semiconductor device includes a first semiconductor chip operating at a first power supply voltage and a second semiconductor chip operating at a second power supply voltage lower than the first power supply voltage to supply the second power supply voltage to the first semiconductor chip. The semiconductor chips according to the present invention are conveniently used for fabrication of the semiconductor device. The first semiconductor chip includes an output circuit including a first transistor and a second transistor, interconnected in series and turned on or off complementarily. The output circuit outputs a signal to a first external output terminal. The first semiconductor chip also includes a third transistor connected in series with the first and second transistors and having a gate electrode connected to a second output terminal. The entire chip area is reduced, as compared with the case where plural semiconductor chips, operated at different operating voltages, are interconnected and used as such in a semiconductor device provided with an input/output buffer operating at a voltage different from the respective operating voltages resulting in an increased chip area.
摘要翻译：半导体器件包括以第一电源电压工作的第一半导体芯片和以低于第一电源电压的第二电源电压工作的第二半导体芯片，以向第一半导体芯片提供第二电源电压。根据本发明的半导体芯片方便地用于制造半导体器件。第一半导体芯片包括一个包括第一晶体管和第二晶体管的输出电路，其互相串联并互补地开或关。输出电路将信号输出到第一外部输出端子。第一半导体芯片还包括与第一和第二晶体管串联连接的第三晶体管，并且具有连接到第二输出端子的栅电极。与在不同工作电压下工作的多个半导体芯片相互连接并将其用于半导体器件的情况相比，整个芯片面积减小，该半导体器件具有以不同于各个工作电压的电压工作的输入/输出缓冲器导致芯片面积增加。

6. 发明申请

US20050156616A1 Integrated circuit device 有权
标题翻译：集成电路器件
公开(公告)号：US20050156616A1
公开(公告)日：2005-07-21
申请号：US11036980
申请日：2005-01-19
申请人： Yoshiaki Morishita , Nobuteru Oh , Tomoaki Isozaki
发明人： Yoshiaki Morishita , Nobuteru Oh , Tomoaki Isozaki
IPC分类号： H01L25/18 , G01R31/02 , G01R31/317 , G11C29/00 , G11C29/12 , G11C29/48 , H01L21/822 , H01L25/065 , H01L25/07 , H01L27/04
CPC分类号： G11C29/1201 , G01R31/31701 , G01R31/31723 , G11C29/48 , G11C2029/0401 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73207 , H01L2225/06513 , H01L2225/06596 , H01L2924/00014 , H01L2924/01079 , H01L2924/15311 , H01L2224/05599
摘要： The integrated circuit device includes a memory chip and a logic chip. The memory chip has memory I/O pads and test pads. The test pads are placed in line at the position outer than memory I/O pads and larger than the memory I/O pads. The logic chip has logic COC I/O pads. The logic COC I/O pads are connected to the memory I/O pads.
摘要翻译：集成电路装置包括存储芯片和逻辑芯片。存储器芯片具有存储器I / O焊盘和测试焊盘。测试焊盘放置在比存储器I / O焊盘外部的位置并且大于存储器I / O焊盘的位置。逻辑芯片具有逻辑COC I / O焊盘。逻辑COC I / O焊盘连接到存储器I / O焊盘。

7. 发明授权

US5292687A Process for lay-out of a semiconductor integrated circuit 失效
标题翻译：布线半导体集成电路的工艺
公开(公告)号：US5292687A
公开(公告)日：1994-03-08
申请号：US832331
申请日：1992-02-07
申请人： Tomoaki Isozaki
发明人： Tomoaki Isozaki
IPC分类号： H01L21/60 , G06F17/50 , H01L21/82 , H01L23/485 , H01L23/528
CPC分类号： H01L24/06 , H01L23/528 , H01L24/03 , H01L2224/05554 , H01L2924/01015 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/1433
摘要： A pad is provided outside a pad block. The most appropriate position is determined for the pad which is connected to the pad block. The pad block is arranged to be most appropriate in position relative to the pad, and a coordinate of the pad block is determined to be used for interconnection of internal regions of the pad block.
摘要翻译：在垫块外部设置垫。对于连接到焊盘块的焊盘确定最合适的位置。衬垫块布置成相对于衬垫最适合的位置，并且确定焊盘块的坐标用于焊盘块的内部区域的互连。

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